公开(公告)号：US07622769B2

公开(公告)日：2009-11-24

申请号：US11497665

申请日：2006-08-01

申请人： John A. Smythe, III ,  Jigish D. Trivedi

发明人： John A. Smythe, III ,  Jigish D. Trivedi

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L21/76224

摘要： A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, an oxygen barrier is deposited into the trench. An expandable, oxidizable liner, preferably amorphous silicon, is then deposited. The trench is then filled with a spin-on dielectric (SOD) material. A densification process is then applied, whereby the SOD material contracts and the oxidizable liner expands. Preferably, the temperature is ramped up while oxidizing during at least part of the densification process. The resulting trench has a negligible vertical wet etch rate gradient and a negligible recess at the top of the trench.

摘要翻译： 提供了将电介质材料沉积到亚微米空间和结构中的方法。 在晶片的表面中蚀刻沟槽之后，将氧势垒沉积到沟槽中。 然后沉积可膨胀的可氧化衬垫，优选非晶硅。 然后用旋涂电介质（SOD）材料填充沟槽。 然后施加致密化过程，由此SOD材料收缩并且可氧化衬里膨胀。 优选地，在致密化过程的至少部分期间，温度升高而氧化。 所形成的沟槽具有可忽略的垂直湿蚀刻速率梯度和在沟槽顶部的可忽略的凹陷。

公开(公告)号：US20090190394A1

公开(公告)日：2009-07-30

申请号：US12421950

申请日：2009-04-10

申请人： Suraj Mathew ,  Jigish D. Trivedi

发明人： Suraj Mathew ,  Jigish D. Trivedi

IPC分类号： G11C11/24 ,  H01L21/8242

CPC分类号： G11C7/00 ,  H01L21/84 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10882 ,  H01L27/1203 ,  H01L29/7841

摘要： A method of forming capacitorless DRAM over localized silicon-on-insulator comprises the following steps: A silicon substrate is provided, and an array of silicon studs is defined within the silicon substrate. An insulator layer is defined atop at least a portion of the silicon substrate, and between the silicon studs. A silicon-over-insulator layer is defined surrounding the silicon studs atop the insulator layer, and a capacitorless DRAM is formed within and above the silicon-over-insulator layer.

摘要翻译： 在局部绝缘体上形成无电容器DRAM的方法包括以下步骤：提供硅衬底，并且硅衬底阵列限定在硅衬底内。 绝缘体层限定在硅衬底的至少一部分之上，并且在硅柱之间。 围绕绝缘体层上方的硅柱的绝缘体层被限定，并且在绝缘体上硅层内部和上方形成无电容的DRAM。

公开(公告)号：US07384849B2

公开(公告)日：2008-06-10

申请号：US11090529

申请日：2005-03-25

申请人： Kunal R. Parekh ,  Suraj Mathew ,  Jigish D. Trivedi ,  John K. Zahurak ,  Sanh D. Tang

发明人： Kunal R. Parekh ,  Suraj Mathew ,  Jigish D. Trivedi ,  John K. Zahurak ,  Sanh D. Tang

IPC分类号： H01L21/336

CPC分类号： H01L27/10876 ,  H01L27/10823

摘要： The invention includes methods of forming recessed access devices. A substrate is provided to have recessed access device trenches therein. A pair of the recessed access device trenches are adjacent one another. Electrically conductive material is formed within the recessed access device trenches, and source/drain regions are formed proximate the electrically conductive material. The electrically conductive material and source/drain regions together are incorporated into a pair of adjacent recessed access devices. After the recessed access device trenches are formed within the substrate, an isolation region trench is formed between the adjacent recessed access devices and filled with electrically insulative material to form a trenched isolation region.

摘要翻译： 本发明包括形成凹入进入装置的方法。 提供基板以在其中具有凹入的接入装置沟槽。 一对凹进的接入设备沟槽彼此相邻。 导电材料形成在凹进的存取装置沟槽内，源极/漏极区域靠近导电材料形成。 导电材料和源极/漏极区域一起被并入一对相邻的凹进入器件中。 在凹陷的访问设备沟槽形成在衬底内之后，在相邻的凹进的访问设备之间形成隔离区沟槽，并且填充有电绝缘材料以形成沟槽隔离区域。

公开(公告)号：US20080113478A1

公开(公告)日：2008-05-15

申请号：US11598449

申请日：2006-11-13

申请人： Kurt D. Beigel ,  Jigish D. Trivedi ,  Kevin G. Duesman

发明人： Kurt D. Beigel ,  Jigish D. Trivedi ,  Kevin G. Duesman

IPC分类号： H01L21/8242

CPC分类号： H01L29/66621 ,  H01L27/10876

摘要： Semiconductor memory devices having recessed access devices are disclosed. In some embodiments, a method of forming the recessed access device includes forming a device recess in a substrate material that extends to a first depth in the substrate that includes a gate oxide layer in the recess. The device recess may be extended to a second depth that is greater that the first depth to form an extended portion of the device recess. A field oxide layer may be provided within an interior of the device recess that extends inwardly into the interior of the device recess and into the substrate. Active regions may be formed in the substrate that abut the field oxide layer, and a gate material may be deposited into the device recess.

摘要翻译： 公开了具有凹入式存取装置的半导体存储器件。 在一些实施例中，形成凹陷进入装置的方法包括在衬底材料中形成器件凹部，该衬底材料延伸到衬底中的第一深度，该第一深度包括凹陷中的栅极氧化物层。 装置凹部可以延伸到大于第一深度的第二深度，以形成装置凹部的延伸部分。 场氧化物层可以设置在器件凹部的内部，其内部延伸到器件凹部的内部并进入衬底。 活性区域可以形成在衬底中，其邻接场氧化物层，并且栅极材料可以沉积到器件凹部中。

公开(公告)号：US07176096B1

公开(公告)日：2007-02-13

申请号：US10631921

申请日：2003-07-31

申请人： Jigish D. Trivedi

发明人： Jigish D. Trivedi

IPC分类号： H01L21/336 ,  H01L21/3205 ,  H01L21/44

CPC分类号： H01L23/485 ,  H01L21/76895 ,  H01L21/823475 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a local interconnect for a semiconductor integrated circuit, the local interconnect comprising a refractory silicide contact having a substantially small sheet resistance formed at an exhumed surface of a gate stack, wherein the local interconnect electrically couples a gate electrode of the gate stack with an active region of the semiconductor substrate. The method of forming the local interconnect comprises depositing a gate oxide layer over the substrate, a first polysilicon layer over the gate oxide layer, a laterally conducting layer over the polysilicon layer, a second polysilicon layer over the laterally conducting layer, and an insulating layer over the second polysilicon layer. The intermediate structure is then etched so as to form a plurality of gate stacks. A surface of the second polysilicon layer of a gate stack is exhumed so as to allow subsequent formation of the refractory silicide contact at the exhumed surface. A plurality of spacers are formed along the vertical surfaces of the gate stacks and the substrate is selectively doped so as to form active regions within the substrate. A layer of titanium is deposited over the substrate and a silicon source and/or hardmask material layer is deposited over the titanium layer so as to extend between the gate electrode and the active region of the silicon. The mask layer is then patterned in an etching process so that the mask layer defines the extent of the local interconnect structure. The intermediate structure is then exposed to a high temperature N2/NH3 ambient which induces the formation of refractory silicide contacts at the exhumed surface of the polysilicon layer of the gate stack and at the active region of the substrate as well as the formation of refractory nitride (TiN) at the exposed portions of the titanium layer. A selective wet etch follows which removes the exposed unreacted titanium and exposed titanium nitride and leaves behind the local interconnect.

公开(公告)号：US06724089B2

公开(公告)日：2004-04-20

申请号：US10317265

申请日：2002-12-11

申请人： Jigish D. Trivedi ,  Mike P. Violette

发明人： Jigish D. Trivedi ,  Mike P. Violette

IPC分类号： H01L28528

CPC分类号： H01L21/76877 ,  H01L21/28562 ,  H01L21/76879

摘要： A dual damascene process is disclosed, in which a contact via and trench pattern is etched into insulating layer(s). The via is first partially filled by selective metal (e.g., tungsten) deposition, thereby forming a partial plug that raises the floor and reduces the effective aspect ratio of the trench and via structure. The remaining portion of the contact via is then filled with a more conductive material (e.g., aluminum). This deposition also at least partially fills the overlying trench to form metal runners. In the illustrated embodiment, hot aluminum deposition fills the portion of the contact via left unoccupied by the selective deposition and overfills into the trench. A further, cold aluminum deposition then follows, topping off the trench prior to planarization. The dual damascene structure thus exhibits a raised floor relative to conventional dual damascene metallization, while still retaining the conduction benefits of aluminum through a significant portion of the contact and the metal runner formed in the trench.

摘要翻译： 公开了一种双镶嵌工艺，其中接触通孔和沟槽图案被蚀刻到绝缘层中。 首先通过选择性金属（例如钨）沉积来部分地填充通孔，从而形成部分插头，其使地板上升并降低沟槽和通孔结构的有效纵横比。 接触通孔的剩余部分然后用更导电的材料（例如铝）填充。 该沉积还至少部分地填充上覆的沟槽以形成金属流道。 在所示实施例中，热铝沉积通过左侧未被占用的选择性沉积填充接触部分，并且过度填充到沟槽中。 然后再进行冷铝沉积，然后在平坦化之前将沟槽顶起来。 因此，双镶嵌结构相对于传统的双镶嵌金属化显示出高的地板，同时仍然保持铝通过形成在沟槽中的大部分接触和金属流道的传导优点。

公开(公告)号：US06594172B2

公开(公告)日：2003-07-15

申请号：US09988960

申请日：2001-11-19

申请人： Todd Abbott ,  Jigish D. Trivedi ,  Mike Violette ,  Chuck Dennison

发明人： Todd Abbott ,  Jigish D. Trivedi ,  Mike Violette ,  Chuck Dennison

IPC分类号： H01L2900

CPC分类号： H01L21/76897 ,  H01L21/76889 ,  H01L21/76895 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10894 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1116

摘要： The invention includes a method of fabricating a circuit in a manner to place certain structures within a predefined distance of one another. Electrical connections are formed between certain structures of silicon, by annealing a conductive material to cause silicon out-diffusing to form local interconnects. The silicon out-diffusion can be facilitated without a masking step thereby simplifying as well as speeding up the fabrication process. The invention also includes a local interconnect thus formed.

公开(公告)号：US06570232B2

公开(公告)日：2003-05-27

申请号：US09999557

申请日：2001-10-19

申请人： Jigish D. Trivedi ,  Michael P. Violette

发明人： Jigish D. Trivedi ,  Michael P. Violette

IPC分类号： H01L2976

CPC分类号： H01L21/76895 ,  H01L23/53257 ,  H01L2924/0002 ,  H01L2924/00

摘要： A process for making a local interconnect and the structures formed thereby. The process is practiced by forming a Ti layer having a nitrogen-rich upper portion over a portion of a substrate, forming a refractory metal layer on the Ti layer, forming a Si layer on the refractory metal layer, removing a portion of the Si layer, and heating to form a local interconnect structure. During this process, a source structure for the local interconnect is formed. This source structure comprises a Ti layer having a nitrogen-rich upper portion overlying a portion of a substrate, a refractory metal layer overlying the Ti layer, and a silicon layer overlying the refractory metal layer. The resulting local interconnect comprises a titanium silicide layer disposed on a portion of a substrate, a nitrogen-rich Ti layer disposed on the titanium silicide layer, and a refractory metal silicide layer disposed on the nitrogen-rich Ti layer. The local interconnect is especially useful for reducing cratering and consumption of silicon regions underlying the local interconnect.

公开(公告)号：US06522001B2

公开(公告)日：2003-02-18

申请号：US10024256

申请日：2001-12-17

申请人： Jigish D. Trivedi

发明人： Jigish D. Trivedi

IPC分类号： H01L2348

CPC分类号： H01L21/32053 ,  H01L21/28518 ,  H01L21/76895 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides methods of forming local interconnect structures for integrated circuits. A representative embodiment includes depositing a silicon source layer over a substrate having at least one topographical structure thereon. The silicon source layer preferably comprising silicon rich silicon nitride, silicon oxynitride or other silicon source having sufficient free silicon to form a silicide but not so much free silicon as to result in formation of stringers (i.e., does not comprise polysilicon). The silicon source layer is preferably deposited over an active area in the substrate and at least a portion of the topographical structure. A silicide forming material, e.g., a refractory metal, is deposited directly on selected regions of the silicon source layer and over the topographical structure. A silicide layer is made from the silicide forming material and the silicon source layer preferably by annealing the structure. The silicide layer defines a portion of the local interconnect structure, unreacted silicide forming material is removed and an interlevel dielectric is formed over the silicide layer. The interlevel dielectric includes a recess defined substantially over the active area and an electrically conductive material is deposited in the recess. The present invention also provides local interconnect structures.

公开(公告)号：US06482689B2

公开(公告)日：2002-11-19

申请号：US09892956

申请日：2001-06-27

申请人： Jigish D. Trivedi

发明人： Jigish D. Trivedi

IPC分类号： H01L218238

CPC分类号： H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming stacked local interconnects that do not extend into higher levels within a multilevel IC device for economizing space available within the IC device and increasing design flexibility. In one embodiment, the method of the present invention provides a stacked local interconnect which electrically connects a first group of interconnected electrical features with one or more additional isolated groups of interconnected electrical features or one or more isolated individual electrical features. In a second embodiment, the method of the present invention provides a stacked local interconnect which electrically connects an individual electrical feature to one or more additional isolated electrical features.