利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

48 条记录 (耗时 0.033 秒)

    Suppression of cross diffusion and gate depletion
    4.
    发明申请
    Suppression of cross diffusion and gate depletion 审中-公开
    抑制交叉扩散和栅极耗尽

    公开(公告)号：US20050266666A1

    公开(公告)日：2005-12-01

    申请号：US11191512

    申请日：2005-07-28

    申请人： Jigish Trivedi ,  Zhongze Wang ,  Chih-Chen Cho ,  Mike Violette ,  Todd Abbott

    发明人： Jigish Trivedi ,  Zhongze Wang ,  Chih-Chen Cho ,  Mike Violette ,  Todd Abbott

    IPC分类号： G11C11/412 ,  H01L21/8238 ,  H01L21/8244 ,  H01L27/11

    CPC分类号： G11C11/412 ,  H01L21/823842 ,  H01L21/823871 ,  H01L21/823878 ,  H01L27/11 ,  H01L27/1104

    摘要： According to the present invention, an ultrathin buried diffusion barrier layer (UBDBL) is formed over all or part of the doped polysilicon layer of a polysilicide structure composed of the polycrystalline silicon film and an overlying film of a metal, metal silicide, or metal nitride. More specifically, according to one embodiment of the present invention, a memory cell is provided comprising a semiconductor substrate, a P well, an N well, an N type active region, a P type active region, an isolation region, a polysilicide gate electrode structure, and a diffusion barrier layer. The P well is formed in the semiconductor substrate. The N well is formed in the semiconductor substrate adjacent to the P well. The N type active region is defined in the P well and the P type active region is defined in the N well. The isolation region is arranged to isolate the N type active region from the P type active region. The polysilicide gate electrode structure is composed of a polycrystalline silicon film and an overlying metal, metal silicide, or metal nitride film. The polycrystalline silicon film comprises an N+ polysilicon layer formed with the N type active region and a P+ polysilicon layer formed with the P type active region. The diffusion barrier layer is formed in the polysilicide gate electrode structure over a substantial portion of the polycrystalline silicon film between the polycrystalline silicon film and the metal, metal silicide, or metal nitride film.

    摘要翻译： 根据本发明，在由多晶硅膜和金属，金属硅化物或金属氮化物的覆盖膜构成的多晶硅结构的全部或部分掺杂多晶硅层上形成超薄掩埋扩散阻挡层（UBDBL） 。 更具体地，根据本发明的一个实施例，提供了一种存储单元，其包括半导体衬底，P阱，N阱，N型有源区，P型有源区，隔离区，多晶硅栅电极 结构和扩散阻挡层。 P阱形成在半导体衬底中。 N阱形成在与P阱相邻的半导体衬底中。 N型有源区定义在P阱中，P型有源区定义在N阱中。 隔离区被配置为将N型有源区与P型有源区隔离。 多晶硅栅电极结构由多晶硅膜和上覆金属，金属硅化物或金属氮化物膜构成。 多晶硅膜包括由N型有源区形成的N +多晶硅层和由P型有源区形成的P +多晶硅层。 多晶硅膜与金属，金属硅化物或金属氮化物膜之间的多晶硅膜的大部分上的多硅化物栅电极结构中形成扩散阻挡层。

    Resistive memory device
    9.
    发明授权
    Resistive memory device 失效
    电阻式存储器件

    公开(公告)号：US07397689B2

    公开(公告)日：2008-07-08

    申请号：US11501598

    申请日：2006-08-09

    申请人： Jun Liu ,  Glen Hush ,  Mike Violette ,  Mark Ingram

    发明人： Jun Liu ,  Glen Hush ,  Mike Violette ,  Mark Ingram

    IPC分类号： G11C11/00

    CPC分类号： G11C13/0007 ,  G11C13/0004 ,  G11C13/004 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/79

    摘要： A system having a memory cell. In certain embodiments, the memory cell includes a resistive memory element, an access transistor having a gate, a first terminal, and a second terminal, and a control transistor having a gate, a first terminal, and a second terminal. The first terminal of the access transistor may be coupled to the resistive memory element, and the gate of the access transistor may be coupled to the gate of the control transistor. Additionally, the first terminal of the control transistor may be coupled to the resistive memory element.

    摘要翻译： 具有存储单元的系统。 在某些实施例中，存储单元包括电阻存储器元件，具有栅极，第一端子和第二端子的存取晶体管，以及具有栅极，第一端子和第二端子的控制晶体管。 存取晶体管的第一端可以耦合到电阻性存储器元件，并且存取晶体管的栅极可以耦合到控制晶体管的栅极。 另外，控制晶体管的第一端可以耦合到电阻性存储元件。

    Method of forming a LOCOS trench isolation structure
    10.
    发明授权
    Method of forming a LOCOS trench isolation structure 失效
    形成LOCOS沟槽隔离结构的方法

    公开(公告)号：US6090685A

    公开(公告)日：2000-07-18

    申请号：US916475

    申请日：1997-08-22

    申请人： Fernando Gonzales ,  Mike Violette ,  Nanseng Jeng ,  Aftab Ahmad ,  Klaus Schuegraf

    发明人： Fernando Gonzales ,  Mike Violette ,  Nanseng Jeng ,  Aftab Ahmad ,  Klaus Schuegraf

    IPC分类号： H01L21/762 ,  H01L21/76

    CPC分类号： H01L21/76202 ,  H01L21/76221 ,  Y10S148/05

    摘要： A semiconductor structure pad oxide layer is enlarged by local oxidation of silicon to form a field oxide. An etchback causes the thinnest portions of the field oxide to recede such that a portion of the semiconductor substrate is exposed. An etch through the exposed portion of the semiconductor substrate forms a microtrench between the field oxide and the nitride layer with a lateral dimension that is less than that currently achievable by conventional photolithography. The microtrench is then filled by oxide or nitride growth or by deposition of a dielectric material. In another embodiment, formation of the microtrench is carried out as set forth above, but the nitride layer is removed immediately following trench formation. Alternatively, the pad oxide layer is stripped and a new oxide layer is regrown that substantially covers all exposed surfaces of active areas of the semiconductor substrate. The regrown oxide layer will encroach into all exposed surfaces of active areas and will grow also in the microtrench. Alternatively, the pad oxide layer is etched substantially uniformly at regions distant from nitride layer, whereas the etchant concentrates the etch against the nitride layer such that etching is accelerated at this location. Because of accelerated etching at this location, a breach in the pad oxide layer forms before etching of the pad oxide layer has been generally penetrated. The breach has a width of sub-photolithographic limits preparatory to formation of a microtrench thereunder.

    摘要翻译： 通过硅的局部氧化来扩大半导体结构衬垫氧化物层以形成场氧化物。 回蚀使场氧化物的最薄部分后退，使得半导体衬底的一部分露出。 通过半导体衬底的暴露部分的蚀刻在场氧化物和氮化物层之间形成微切口，其横向尺寸小于通过常规光刻法目前可实现的横向尺寸。 然后通过氧化物或氮化物生长或通过沉积电介质材料来填充微切口。 在另一个实施例中，微沟槽的形成如上所述进行，但是在形成沟槽之后立即去除氮化物层。 或者，剥除焊盘氧化物层，并重新生长新的氧化物层，其基本上覆盖半导体衬底的有源区域的所有暴露表面。 再生的氧化物层将侵蚀到活性区域的所有暴露表面，并且还将在微型扳手中生长。 或者，在远离氮化物层的区域处基本上均匀地蚀刻焊盘氧化物层，而蚀刻剂将蚀刻集中到氮化物层上，使得在该位置加速蚀刻。 由于在该位置处的加速蚀刻，在氧化垫层的蚀刻之前形成的衬垫氧化物层中的破裂已经被普遍渗透。 该破裂具有准备在其下形成微型切割器的副光刻极限的宽度。