公开(公告)号：US08572306B2

公开(公告)日：2013-10-29

申请号：US13089834

申请日：2011-04-19

Applicant: Jiin Lai ,  Chin-Sung Hsu ,  Terrance Shiyang Shih ,  Jinkuan Tang ,  Buheng Xu ,  Hui Jiang

Inventor： Jiin Lai ,  Chin-Sung Hsu ,  Terrance Shiyang Shih ,  Jinkuan Tang ,  Buheng Xu ,  Hui Jiang

IPC: G06F13/36 ,  G06F13/40

CPC classification number: G06F13/4059 ,  G06F13/4291

Abstract: The present invention is directed to a universal serial bus (USB) transaction translator and a micro-frame synchronization method. A device interface is coupled to a device via a device bus, and a host interface is coupled to a host via a host bus, wherein the host USB version is higher than the device USB version. At least two buffers configured to store data are disposed between the device interface and the host interface. A controller stores the data in the buffers alternately. A start-of-frame (SOF) counter is used to count the SOF packets, wherein the counting value of the SOF counter is compared to a predefined value. Specifically, the controller resets a SOF timer for sending the SOF packet when the counting value achieves the predefined value or is greater than the predefined value, such that the SOF packet and an isochronous timestamp packet (ITP) from the host are sent at the same time. Further, the controller delays the sending of the SOF packet for a period of time according to the ITP from the host. In another embodiment, the sending period of SOF packets may be dynamically adjusted in isochronous transfer.

Abstract translation: 本发明涉及通用串行总线（USB）事务转换器和微帧同步方法。 设备接口经由设备总线耦合到设备，并且主机接口通过主机总线耦合到主机，其中主机USB版本高于设备USB版本。 配置为存储数据的至少两个缓冲器被布置在设备接口和主机接口之间。 控制器交替地将数据存储在缓冲器中。 使用起始帧（SOF）计数器对SOF分组进行计数，其中将SOF计数器的计数值与预定义的值进行比较。 具体地，当计数值达到预定义值或大于预定值时，控制器复位用于发送SOF分组的SOF定时器，使得来自主机的SOF分组和等时时间戳分组（ITP）以相同的方式发送 时间。 此外，控制器根据来自主机的ITP延迟SOF分组的发送一段时间。 在另一个实施例中，SOF分组的发送周期可以在等时传输中动态调整。

公开(公告)号：US08521031B2

公开(公告)日：2013-08-27

申请号：US12950122

申请日：2010-11-19

Applicant: Jinkuan Tang ,  Jiin Lai

Inventor： Jinkuan Tang ,  Jiin Lai

IPC: H04B10/02 ,  H04B1/00 ,  G02B6/26

CPC classification number: H04B10/40

Abstract: An optical transceiver module includes a receiving unit, a transmission driving unit, and a terminal control unit. The receiving unit outputs a receiver lost signal. The transmission driving unit includes a positive receiving signal terminal and a negative receiving signal terminal. The terminal control unit is coupled between the positive receiving signal terminal and the negative receiving signal terminal. The terminal control unit controls whether a differential terminator impedance is coupled between the positive receiving signal terminal and the negative receiving signal terminal according to the receiver lost signal.

Abstract translation: 光收发模块包括接收单元，传输驱动单元和终端控制单元。 接收单元输出接收机丢失信号。 发送驱动单元包括正接收信号端子和负接收信号端子。 终端控制单元耦合在正接收信号端子和负接收信号端子之间。 终端控制单元根据接收机丢失信号来控制差分终端阻抗是否连接在正接收信号端子和负接收信号端子之间。

公开(公告)号：US08499174B2

公开(公告)日：2013-07-30

申请号：US12358412

申请日：2009-01-23

Applicant: Jiin Lai ,  Chung-Che Wu

Inventor： Jiin Lai ,  Chung-Che Wu

IPC: G06F1/00

CPC classification number: G06F1/3203 ,  G06F1/3275 ,  Y02D10/13 ,  Y02D10/14

Abstract: Resuming from a sleep state. A request may received to resume operation of a computer system from a sleep state to an executing state. A restoring process may be initiated to restore the computer system to an executing state. The restoring process may include loading information from a nonvolatile memory medium to a computer system memory medium. A request may be received from a processor of the computer system to access the computer system memory medium. The request may require access to a portion of the computer system memory medium in the executing state, and may be received prior to completion of the restoring process. It may be determined if the portion of the computer system memory medium has been restored. If the portion of the computer system memory medium has not been restored, the portion of the computer system memory medium may be restored from the nonvolatile memory medium ahead of other portions in the restoring process.

Abstract translation: 从睡眠状态恢复。 可以接收请求以恢复计算机系统从睡眠状态到执行状态的操作。 可以启动恢复过程以将计算机系统恢复到执行状态。 恢复过程可以包括将信息从非易失性存储介质加载到计算机系统存储介质。 可以从计算机系统的处理器接收请求以访问计算机系统存储介质。 该请求可能需要访问处于执行状态的计算机系统存储介质的一部分，并且可以在恢复处理完成之前被接收。 可以确定计算机系统存储介质的部分是否已被恢复。 如果计算机系统存储介质的部分尚未被恢复，那么计算机系统存储介质的该部分可以在恢复过程中的其它部分之前从非易失性存储介质中恢复。

公开(公告)号：US08473665B2

公开(公告)日：2013-06-25

申请号：US12959261

申请日：2010-12-02

Applicant: Jinkuan Tang ,  Jiin Lai ,  Buheng Xu ,  Hui Jiang

Inventor： Jinkuan Tang ,  Jiin Lai ,  Buheng Xu ,  Hui Jiang

IPC: G06F13/20 ,  G06F13/38

CPC classification number: G06F13/385 ,  G06F13/387

Abstract: The present invention is directed to a universal serial bus (USB) transaction translator and an associated IN isochronous transaction method. A device interface is coupled to a device via a device bus, and a host interface is coupled to a host via a host bus, wherein the host USB version is higher than the device USB version. At least two buffers configured to store data are disposed between the device interface and the host interface. A controller stores the data in the buffers alternately. A register is used to record device bus information. Before the host sends an IN packet, the controller pre-fetches data from the device according to the device bus information and then stores the data in the buffers; the controller responds with the pre-fetched data to the host after the host sends the IN packet.

Abstract translation: 本发明涉及通用串行总线（USB）事务转换器和相关的IN等时事务处理方法。 设备接口经由设备总线耦合到设备，并且主机接口通过主机总线耦合到主机，其中主机USB版本高于设备USB版本。 配置为存储数据的至少两个缓冲器被布置在设备接口和主机接口之间。 控制器交替地将数据存储在缓冲器中。 寄存器用于记录设备总线信息。 在主机发送IN数据包之前，控制器根据设备总线信息从设备预取数据，然后将数据存储在缓冲区中; 在主机发送IN数据包之后，控制器会将预取的数据作为响应。

公开(公告)号：US08417853B2

公开(公告)日：2013-04-09

申请号：US12906431

申请日：2010-10-18

Applicant: Di Dai ,  Jiin Lai ,  Zhiqiang Hui ,  Shanna Pang

Inventor： Di Dai ,  Jiin Lai ,  Zhiqiang Hui ,  Shanna Pang

IPC: G06F3/00 ,  G06F5/00

CPC classification number: G06F13/385

Abstract: A USB host control method is provided for a USB host controller. The USB host controller includes a USB device and a buffer, the USB device includes one or more endpoints. The USB host control method includes the steps of: storing first output data to be sent to a first endpoint into one or more buffer units used for the first endpoint; sending the first output data to the first endpoint; and when a first predetermined response from the first endpoint is received, configuring fake releasing labels and information tags corresponding to the first endpoint in the one or more buffer units, and not releasing the one or more buffer units.

Abstract translation: USB主机控制器提供USB主机控制方式。 USB主机控制器包括USB设备和缓冲器，USB设备包括一个或多个端点。 USB主机控制方法包括以下步骤：将要发送到第一端点的第一输出数据存储为用于第一端点的一个或多个缓冲单元; 将第一输出数据发送到第一端点; 并且当接收到来自所述第一端点的第一预定响应时，配置与所述一个或多个缓冲器单元中的所述第一端点对应的假释放标签和信息标签，并且不释放所述一个或多个缓冲器单元。

公开(公告)号：US20120008938A1

公开(公告)日：2012-01-12

申请号：US12940347

申请日：2010-11-05

Applicant: Jinkuan Tang ,  Jiin Lai ,  Hao-Hsuan Chiu

Inventor： Jinkuan Tang ,  Jiin Lai ,  Hao-Hsuan Chiu

IPC: H04B10/00 ,  H04B10/08

CPC classification number: H04B10/03

Abstract: A data transmission system and method are provided. The data transmission system includes a first link partner and an optical transceiver unit. The first link partner includes a controller. When the first link partner is in an abnormal operation mode, the controller controls the first link partner to exit from the abnormal operation mode. The optical transceiver unit is coupled between the first link partner and a second link partner and performs data transmission between the first link partner and the second link partner. According to the data transmission system and method, one link partner can accurately detect whether another link partner is coupled to the one link partner through an optical transceiver unit. Accordingly, data transmission between the two link partners can be stably performed through the optical transceiver unit.

Abstract translation: 提供了一种数据传输系统和方法。 数据传输系统包括第一链路伙伴和光收发器单元。 第一个链路伙伴包括一个控制器。 当第一链路伙伴处于异常操作模式时，控制器控制第一链路伙伴退出异常操作模式。 光收发器单元耦合在第一链路伙伴和第二链路伙伴之间，并在第一链路伙伴和第二链路伙伴之间执行数据传输。 根据数据传输系统和方法，一个链路伙伴可以准确地检测另一个链路伙伴是否通过光收发器单元耦合到一个链路伙伴。 因此，可以通过光收发器单元稳定地执行两个链路伙伴之间的数据传输。

公开(公告)号：US20080100636A1

公开(公告)日：2008-05-01

申请号：US11554769

申请日：2006-10-31

Applicant: Jiin Lai ,  Chin-Hwaun Wu ,  Ching-Hsiang Lin ,  Chin-Huei Wang

Inventor： Jiin Lai ,  Chin-Hwaun Wu ,  Ching-Hsiang Lin ,  Chin-Huei Wang

IPC: G09G5/397

CPC classification number: G09G5/39 ,  G09G2330/021 ,  G09G2360/125

Abstract: A computer system having low-power operation includes a controller in communication with a first storage device and a second storage device. The controller can be configured to periodically retrieve dynamic frame data from a first storage device during a time period when the computer system is not in an idle state. During a time period when the computer system is in an idle state, the controller is configured to store static frame data into a second storage device, and repeatedly retrieve the static frame data from the second storage device to display an image represented by the static frame data during a time when the computer system continues to be in the idle state.

Abstract translation: 具有低功率操作的计算机系统包括与第一存储设备和第二存储设备通信的控制器。 控制器可以被配置为在计算机系统不处于空闲状态的时间段内从第一存储设备周期性地检索动态帧数据。 在计算机系统处于空闲状态的时间段期间，控制器被配置为将静态帧数据存储到第二存储设备中，并且从第二存储设备重复地检索静态帧数据以显示由静态帧表示的图像 在计算机系统继续处于空闲状态的时间期间的数据。

公开(公告)号：US20080100606A1

公开(公告)日：2008-05-01

申请号：US11554787

申请日：2006-10-31

Applicant: Ruei-Ling Lin ,  Jiin Lai ,  Win Sheng-Cheng

Inventor： Ruei-Ling Lin ,  Jiin Lai ,  Win Sheng-Cheng

IPC: G09G5/00

CPC classification number: G09G5/00 ,  G09G2330/022

Abstract: Included are systems and methods for reducing power consumption in a computer system. At least one embodiment of a method, among others, includes processing data in a normal mode, receiving an indication of a transition into an idle mode, capturing at least one frame of display data, and transmitting the captured frame of display data for display during idle mode.

Abstract translation: 包括用于降低计算机系统功耗的系统和方法。 方法的至少一个实施例包括在正常模式下处理数据，接收转换到空闲模式的指示，捕获至少一帧显示数据，以及发送所捕获的显示数据帧以便在 空闲模式

公开(公告)号：US07356632B2

公开(公告)日：2008-04-08

申请号：US11402700

申请日：2006-04-11

Applicant: Bi-Yun Yeh ,  Jiin Lai ,  Sheng-Chung Wu

Inventor： Bi-Yun Yeh ,  Jiin Lai ,  Sheng-Chung Wu

IPC: G06F13/14 ,  G06F12/00 ,  G06F1/32

CPC classification number: G06F13/1668 ,  G06F13/4243 ,  Y02D10/14 ,  Y02D10/151

Abstract: The present invention provides a data memory controller that supports for the invert of data bus. Data transmitted from a memory is received in a chip set, which further transmits the data to a data processing apparatus. While receiving the memory data, the chip set doubles the bandwidth and reduces the frequency, such that the time margin for processing data is increased. In addition, after outputting data to the data processing apparatus, a first frame of data is compared to bus idle state to further reduce frequency of data invert and power consumption.

Abstract translation: 本发明提供一种支持数据总线反转的数据存储控制器。 从存储器发送的数据被接收在芯片组中，其进一步将数据发送到数据处理装置。 在接收存储器数据的同时，芯片组将带宽加倍并降低频率，使得处理数据的时间裕度增加。 此外，在向数据处理装置输出数据之后，将第一帧数据与总线空闲状态进行比较，以进一步降低数据反转和功耗的频率。

公开(公告)号：US07231560B2

公开(公告)日：2007-06-12

申请号：US10985461

申请日：2004-11-10

Applicant: Jiin Lai ,  Wayne Tseng

Inventor： Jiin Lai ,  Wayne Tseng

IPC: G01R31/28 ,  G06F11/00

CPC classification number: G01R31/31716 ,  G01R31/043 ,  G01R31/2815

Abstract: This invention discloses a method for testing at least one physical link on a motherboard associated with an on-board PCI Express device. A test card is connected to an input/output port on the motherboard, wherein the test card has a PCI Express test device. A test pattern is transmitted from the test card to the PCI Express device and receiving a test result pattern by the test card from the PCI Express device through the physical link for testing thereof. The test result pattern is examined to determine defects of the physical link on the motherboard.

Abstract translation: 本发明公开了一种用于测试与板载PCI Express设备相关联的母板上的至少一个物理链路的方法。 测试卡连接到母板上的输入/输出端口，其中测试卡具有PCI Express测试设备。 测试模式从测试卡发送到PCI Express设备，并通过测试卡从PCI Express设备通过物理链路接收测试结果模式，以进行测试。 检查测试结果模式，以确定主板上物理链路的缺陷。