公开(公告)号：US08164179B2

公开(公告)日：2012-04-24

申请号：US12336422

申请日：2008-12-16

Applicant: Kim-Yong Goh ,  Jing-En Luan

Inventor： Kim-Yong Goh ,  Jing-En Luan

IPC: H01L23/12

CPC classification number: H01L23/367 ,  H01L23/04 ,  H01L23/3114 ,  H01L23/552 ,  H01L24/97 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/16152 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A chip scale package (CSP) device includes a CSP having a semiconductor die electrically coupled to a plurality of solder balls. A can having an inside top surface and one or more side walls defines a chamber. The CSP is housed in the chamber and is attached to the inside top surface of the can. A printed circuit board is attached to the solder balls and to the one or more side walls to provide support to the CSP and to the can. The CSP may be a Wafer-Level CSP. The can may be built from a metallic substance or from a non-metallic substance. The can provides stress relief to the CSP during a drop test and during a thermal cycle test.

Abstract translation: 芯片级封装（CSP）器件包括具有电耦合到多个焊球的半导体管芯的CSP。 具有内顶表面和一个或多个侧壁的罐体限定了一个室。 CSP容纳在腔室中，并连接到罐的内部顶部表面。 印刷电路板附接到焊球和一个或多个侧壁以提供对CSP和罐的支撑。 CSP可能是晶片级CSP。 罐可以由金属物质或非金属物质制成。 在跌落测试期间和热循环测试期间，罐可以为CSP提供应力消除。

公开(公告)号：US20120074592A1

公开(公告)日：2012-03-29

申请号：US12893651

申请日：2010-09-29

Applicant: Jing-En Luan

Inventor： Jing-En Luan

IPC: H01L23/48 ,  H01L21/56

CPC classification number: H01L24/97 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/3171 ,  H01L23/552 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/82 ,  H01L25/105 ,  H01L25/16 ,  H01L2224/12105 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/83191 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/12036 ,  H01L2924/14 ,  H01L2224/83 ,  H01L2224/19 ,  H01L2224/82 ,  H01L2924/00

Abstract: An electronic package that includes a composite material base. In one embodiment the electronic package is an expanded wafer-level package. The composite material base is composed of woven strands and polymer material. In one embodiment the composite material base is composed of woven fiberglass strands and an epoxy material. In various embodiments the package includes an electronic circuitry layer on one or another face of the composite material base. In other embodiments conductive vias connect the circuitry layers, including a redistribution layer. In yet another embodiment an electronic package is mounted on the composite material base and electrically couples to the circuit of the expanded wafer-level package. The package having the composite material base is mechanically stronger and can be made thinner than a package that relies on an encapsulant material for structure, and resists cracking.

Abstract translation: 一种包括复合材料基底的电子封装。 在一个实施例中，电子封装是扩展的晶片级封装。 复合材料基底由编织线和聚合物材料组成。 在一个实施方案中，复合材料基底由编织的玻璃纤维束和环氧材料组成。 在各种实施例中，封装包括在复合材料基底的一个或另一个面上的电子电路层。 在其它实施例中，导电通孔连接电路层，包括再分配层。 在另一个实施例中，电子封装安装在复合材料基底上并电耦合到扩展的晶片级封装的电路。 具有复合材料基底的包装机械地更坚固，并且可以制成比依赖于用于结构的密封剂材料的包装，并且抗龟裂。

公开(公告)号：US20110156250A1

公开(公告)日：2011-06-30

申请号：US12651365

申请日：2009-12-31

Applicant: Kim-Yong Goh ,  Jing-En Luan

Inventor： Kim-Yong Goh ,  Jing-En Luan

IPC: H01L23/498 ,  H01L21/60

CPC classification number: H01L21/565 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/19 ,  H01L24/81 ,  H01L24/96 ,  H01L24/97 ,  H01L25/105 ,  H01L25/16 ,  H01L2221/68345 ,  H01L2221/68377 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/16225 ,  H01L2224/20 ,  H01L2224/81001 ,  H01L2224/81005 ,  H01L2224/81801 ,  H01L2224/97 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/01019 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2924/00

Abstract: A flip-chip fan-out wafer level package for package-on-package applications includes a semiconductor die with solder bumps on an upper surface in a flip chip configuration. The die is inverted, with an upper surface facing an upper side of a redistribution layer, with the solder bumps in electrical contact with respective chip contact pads of the redistribution layer. The redistribution layer includes conductive traces that place each of the solder bumps in electrical contact with one or both of one of a plurality of upper redistribution contact pads and one of a plurality of lower redistribution contact pads. Each of the plurality of upper redistribution contact pads has an upper solder ball in electrical contact therewith. The die and the upper solder balls are at least partially encapsulated in a layer of mold compound positioned on the upper surface of the redistribution layer, and whose lateral dimensions are defined by the lateral dimensions of the redistribution layer. The layer of mold compound has a back-ground surface at which a portion of each of the upper solder balls is exposed, for electrical contact with an upper package. Each of the lower redistribution contact pads has a lower solder ball a coupled thereto.

Abstract translation: 用于封装封装应用的倒装芯片扇出晶片级封装包括在倒装芯片配置的上表面上具有焊料凸块的半导体管芯。 模具倒置，上表面面向再分布层的上侧，焊料凸块与再分布层的相应芯片接触焊盘电接触。 再分配层包括导电迹线，其将每个焊料凸点与多个上再分布接触焊盘和多个下再分布接触焊盘之一中的一个或两者电接触。 多个上再分配接触垫中的每一个具有与其接触的上焊球。 模具和上焊球至少部分地封装在位于再分配层的上表面上的模具化合物层中，并且其横向尺寸由再分布层的横向尺寸限定。 模具化合物层具有背面表面，每个上焊球的一部分暴露在其中，用于与上封装电接触。 每个下再分布接触垫具有与其耦合的较低焊球。