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106 条记录 (耗时 0.018 秒)

    High-k dielectric materials and processes for manufacturing them
    22.
    发明授权
    High-k dielectric materials and processes for manufacturing them 有权
    高k电介质材料及其制造方法

    公开(公告)号：US06451646B1

    公开(公告)日：2002-09-17

    申请号：US09651475

    申请日：2000-08-30

    申请人： Jiong-Ping Lu ,  Ming-Jang Hwang

    发明人： Jiong-Ping Lu ,  Ming-Jang Hwang

    IPC分类号： H01L218242

    CPC分类号： C23C16/34 ,  C23C16/56 ,  H01L21/31604 ,  H01L21/31637 ,  H01L21/31683 ,  H01L27/1085 ,  H01L28/40 ,  H01L28/57

    摘要： High dielectric films of mixed transition metal oxides of titanium and tungsten, or titanium and tantalum, are formed by sequential chemical vapor deposition (CVD) of the respective nitrides and annealing in the presence of oxygen to densify and oxidize the nitrides. The resulting film is useful as a capacitative cell and resists oxygen diffusion to the underlying material, has high capacitance and low current leakage.

    摘要翻译： 通过相应氮化物的顺序化学气相沉积（CVD）形成钛和钨或钛和钽的混合过渡金属氧化物的高介电膜，并在氧的存在下退火以致密化和氧化氮化物。 所得到的膜可用作电容性电池并且抵抗向下层材料的氧扩散，具有高电容和低电流泄漏。

    Method of forming diffusion barriers for copper metallization in integrated cirucits
    23.
    发明授权
    Method of forming diffusion barriers for copper metallization in integrated cirucits 有权
    在集成的铁芯中形成铜金属化的扩散阻挡层的方法

    公开(公告)号：US06245672B1

    公开(公告)日：2001-06-12

    申请号：US09177412

    申请日：1998-10-23

    申请人： Qi-Zhong Hong ,  Wei-Yung Hsu ,  Jiong-Ping Lu ,  Robert H. Havemann

    发明人： Qi-Zhong Hong ,  Wei-Yung Hsu ,  Jiong-Ping Lu ,  Robert H. Havemann

    IPC分类号： H01L214763

    CPC分类号： H01L21/76856 ,  H01L21/76843 ,  H01L21/76855

    摘要： An integrated circuit structure including copper metallization (20, 32, 42), and a method of fabricating the same are disclosed. The structure includes a doped region (7) of a silicon substrate (9), which is typically clad with a metal silicide film (12) formed by way of direct react silicidation. At contact locations (CT) at which the copper metallization (20, 32, 42) is to make contact to the doped region (7), a chemically-densified barrier layer (16, 30, 38) provides a diffusion barrier to the overlying copper metallization (20, 32, 42). The chemically-densified barrier layer (16, 30, 38) is formed by an anneal of the structure to react impurities (14, 28, 36) with the underlying refractory-metal-based film (12, 34); the impurities are introduced by way of wet chemistry, plasma bombardment, or from the ambient in which the structure is annealed.

    摘要翻译： 公开了一种包括铜金属化（20,32,42）的集成电路结构及其制造方法。 该结构包括硅衬底（9）的掺杂区域（7），其通常用通过直接反应硅化形成的金属硅化物膜（12）包覆。 在铜金属化层（20,32,42）将与掺杂区域（7）接触的接触位置（CT）处，化学致密化的势垒层（16,30,38）为覆盖层 铜金属化（20,32,42）。 化学致密化的阻挡层（16,30,38）通过该结构的退火形成，以使杂质（14,28,36）与下面的耐熔金属基膜（12,34）反应; 杂质通过湿化学，等离子体轰击或结构退火的环境引入。

    Nickel silicide formation for semiconductor components
    25.
    发明授权
    Nickel silicide formation for semiconductor components 有权
    半导体元件的硅化镍形成

    公开(公告)号：US08546259B2

    公开(公告)日：2013-10-01

    申请号：US11861421

    申请日：2007-09-26

    申请人： Juanita DeLoach ,  Jiong-Ping Lu ,  Haowen Bu

    发明人： Juanita DeLoach ,  Jiong-Ping Lu ,  Haowen Bu

    IPC分类号： H01L21/44

    CPC分类号： H01L29/665 ,  H01L21/26506 ,  H01L21/28052 ,  H01L21/28518 ,  H01L29/7833

    摘要： Semiconductor components are often fabricated that include a nickel silicide layer, e.g., as part of a gate electrode in a transistor component, which may be formed by forming a layer of nickel on a silicon-containing area of the semiconductor substrate, followed by thermally annealing the semiconductor substrate to produce a nickel silicide. However, nickel may tend to diffuse into silicon during the thermal anneal, and may form crystals that undesirably increase the sheet resistance in the transistor. Carbon may be placed with the nickel to serve as a diffusion suppressant and/or to prevent nickel crystal formation during thermal annealing. Methods are disclosed for utilizing this technique, as well as semiconductor components formed in accordance with this technique.

    摘要翻译： 通常制造半导体部件，其包括硅化镍层，例如，作为晶体管部件中的栅电极的一部分，其可以通过在半导体衬底的含硅区域上形成镍层，然后进行热退火 半导体衬底以产生硅化镍。 然而，镍可能在热退火期间扩散到硅中，并且可能形成不期望地增加晶体管中的薄层电阻的晶体。 碳可以与镍一起放置以用作扩散抑制剂和/或防止在热退火期间形成镍晶体。 公开了利用该技术的方法以及根据该技术形成的半导体部件。

    METHOD OF FORMING A FULLY SILICIDED SEMICONDUCTOR DEVICE WITH INDEPENDENT GATE AND SOURCE/DRAIN DOPING AND RELATED DEVICE
    26.
    发明申请
    METHOD OF FORMING A FULLY SILICIDED SEMICONDUCTOR DEVICE WITH INDEPENDENT GATE AND SOURCE/DRAIN DOPING AND RELATED DEVICE 有权
    形成具有独立栅极和源/漏极掺杂的完全硅化半导体器件的方法及相关器件

    公开(公告)号：US20080265420A1

    公开(公告)日：2008-10-30

    申请号：US11741540

    申请日：2007-04-27

    申请人： Shaofeng Yu ,  Freidoon Mehrad ,  Jiong-Ping Lu

    发明人： Shaofeng Yu ,  Freidoon Mehrad ,  Jiong-Ping Lu

    IPC分类号： H01L21/3205 ,  H01L23/48

    CPC分类号： H01L21/28097 ,  H01L29/66507 ,  H01L29/66545

    摘要： A method of forming a fully silicided semiconductor device with independent gate and source/drain doping and related device. At least some of the illustrative embodiments are methods comprising forming a gate stack over a substrate (the gate stack comprising a polysilicon layer and a blocking layer), and performing an ion implantation into an active region of the substrate adjacent to the gate stack (the blocking layer substantially blocks the ion implantation from the polysilicon layer).

    摘要翻译： 一种形成具有独立栅极和源极/漏极掺杂及相关器件的完全硅化半导体器件的方法。 示例性实施例中的至少一些是包括在衬底上形成栅极堆叠的方法（包括多晶硅层和阻挡层的栅极堆叠），以及执行离子注入到与栅极堆叠相邻的衬底的有源区域中 阻挡层基本上阻挡从多晶硅层的离子注入）。

    Semiconductor device having a silicided gate electrode and method of manufacture therefor
    27.
    发明授权
    Semiconductor device having a silicided gate electrode and method of manufacture therefor 失效
    具有硅化栅电极的半导体器件及其制造方法

    公开(公告)号：US07348265B2

    公开(公告)日：2008-03-25

    申请号：US10790606

    申请日：2004-03-01

    申请人： Jiong-Ping Lu

    发明人： Jiong-Ping Lu

    IPC分类号： H01L21/44 ,  H01L21/4763

    CPC分类号： H01L21/28052 ,  H01L29/6659 ,  H01L29/7833

    摘要： The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the semiconductor device. The semiconductor device (100), among other possible elements, includes a gate oxide (140) located over a substrate (110), and a silicided gate electrode (150) located over the gate oxide (140), wherein the silicided gate electrode (150) includes a first metal and a second metal.

    摘要翻译： 本发明提供一种半导体器件及其制造方法以及包括半导体器件的集成电路。 半导体器件（100）以及其他可能的元件中包括位于衬底（110）上方的栅极氧化物（140）和位于栅极氧化物（140）上方的硅化栅电极（150），其中硅化栅电极 150）包括第一金属和第二金属。

    Process for defect reduction in electrochemical plating
    28.
    发明授权
    Process for defect reduction in electrochemical plating 有权
    电化学电镀中缺陷减少的工艺

    公开(公告)号：US07253124B2

    公开(公告)日：2007-08-07

    申请号：US09971210

    申请日：2001-10-04

    申请人： Jiong-Ping Lu ,  Patricia B. Smith

    发明人： Jiong-Ping Lu ,  Patricia B. Smith

    IPC分类号： H01L21/26

    CPC分类号： H01L21/76864 ,  H01L21/02068 ,  H01L21/321 ,  H01L21/76838 ,  H01L21/76843 ,  H01L21/76873

    摘要： A pre-ECD surface treatment. After forming the barrier material (110) and seed layer (112), the surface of the seed layer (112) is treated with an H2 plasma to remove surface contamination (122), reduce any CuOx (123), and improve wettability. The ECD copper film (124) is then formed over the seed layer (112).

    摘要翻译： 前ECD表面处理。 在形成阻挡材料（110）和种子层（112）之后，种子层（112）的表面用H 2 H 2等离子体处理以除去表面污染物（122），减少任何CuO （123），并提高润湿性。 然后在种子层（112）上形成ECD铜膜（124）。

    Integration scheme for using silicided dual work function metal gates
    30.
    发明授权
    Integration scheme for using silicided dual work function metal gates 有权
    使用硅化双功能金属门的集成方案

    公开(公告)号：US07183187B2

    公开(公告)日：2007-02-27

    申请号：US10851750

    申请日：2004-05-20

    申请人： Jiong-Ping Lu ,  Gregory Shinn ,  Ping Jiang

    发明人： Jiong-Ping Lu ,  Gregory Shinn ,  Ping Jiang

    IPC分类号： H01L21/3205

    CPC分类号： H01L29/66507 ,  H01L21/28097 ,  H01L21/823835 ,  H01L21/823842 ,  H01L27/0811 ,  H01L28/60

    摘要： The present invention provides a method for manufacturing a semiconductor device and a method for manufacturing an integrated circuit including the semiconductor device. The method for manufacturing the semiconductor device, among other possible steps, includes forming a polysilicon gate electrode (250) over a substrate (210) and forming source/drain regions (610) in the substrate (210) proximate the polysilicon gate electrode (250). The method further includes forming a protective layer (710) over the source/drain regions (610) and the polysilicon gate electrode (250), then removing the protective layer (710) from over a top surface of the polysilicon gate electrode (250) while leaving the protective layer (710) over the source/drain regions (250). After the protective layer (710) has been removed from over the top surface of the polysilicon gate electrode (250), the polysilicon gate electrode (250) is silicided to form a silicided gate electrode (1310). The protective layer (710) is also removed from over the source/drain regions (610) and source/drain contact regions (1610) are formed.

    摘要翻译： 本发明提供一种制造半导体器件的方法及其制造方法，该集成电路包括该半导体器件。 除了其他可能的步骤之外，制造半导体器件的方法包括在衬底（210）上形成多晶硅栅电极（250），并在靠近多晶硅栅电极（250）的衬底（210）中形成源/漏区（610） ）。 该方法还包括在源极/漏极区域（610）和多晶硅栅电极（250）之上形成保护层（710），然后从多晶硅栅电极（250）的顶表面上方移除保护层（710） 同时将保护层（710）留在源/漏区（250）上。 在保护层（710）已从多晶硅栅电极（250）的顶表面上方移除之后，多晶硅栅电极（250）被硅化以形成硅化栅电极（1310）。 保护层（710）也从源极/漏极区域（610）上去除并形成源极/漏极接触区域（1610）。