公开(公告)号：US20110291730A1

公开(公告)日：2011-12-01

申请号：US12832549

申请日：2010-07-08

Applicant: Seung-Joon Ahn ,  Jong-Chern Lee

Inventor： Seung-Joon Ahn ,  Jong-Chern Lee

IPC: H03H11/26

CPC classification number: H03K5/135 ,  H03K2005/00104

Abstract: An open loop type delay locked loop includes a delay amount pulse generation unit configured to generate a delay amount pulse having a pulse width corresponding to a delay amount for delay locking a clock signal, a delay amount coding unit configured to output a code value by coding the delay amount in response to the delay amount pulse, a clock control unit configured to adjust a toggling period of the clock signal in response to a control signal, and a delay line configured to delay an adjusted clock signal outputted from the clock control unit in response to the code value.

Abstract translation: 开环型延迟锁定环包括：延迟量脉冲生成单元，被配置为生成具有对应于用于延迟锁定时钟信号的延迟量的脉冲宽度的延迟量脉冲;延迟量编码单元，被配置为通过编码输出代码值 延迟量响应于延迟量脉冲，时钟控制单元，被配置为响应于控制信号调整时钟信号的切换周期;以及延迟线，被配置为将从时钟控制单元输出的经调整的时钟信号延迟 响应代码值。

公开(公告)号：US20110001514A1

公开(公告)日：2011-01-06

申请号：US12624144

申请日：2009-11-23

Applicant: Hyun-Su Yoon ,  Jong-Chern Lee

Inventor： Hyun-Su Yoon ,  Jong-Chern Lee

IPC: H03K19/00

CPC classification number: H04L7/02 ,  H04L7/0045

Abstract: A command control circuit of a semiconductor integrated device includes a plurality of latches sequentially connected and receiving a command signal, and a plurality of selection switches configured to pass or to interrupt the command signal inputted to each one of the plurality of latches.

Abstract translation: 半导体集成装置的指令控制电路包括顺序地连接并接收命令信号的多个锁存器，以及被配置为通过或中断输入到多个锁存器中的每一个的指令信号的多个选择开关。

公开(公告)号：US20060221717A1

公开(公告)日：2006-10-05

申请号：US11176345

申请日：2005-07-08

Applicant: Jong-Chern Lee

Inventor： Jong-Chern Lee

IPC: G11C7/10

CPC classification number: G11C7/1069 ,  G11C7/1051

Abstract: A data output apparatus and method in a global input and output (GIO) line transmits data via the GIO line. This data output apparatus includes a read driver driven responsive to an input of read data for inverting and amplifying the data to output inverted and amplified data onto the GIO line, a GIO termination unit driven responsive to a termination signal for rising or falling a voltage level on the GIO line by a preset level, prior to driving the data onto the GIO line by the read driver, and a receiver driven responsive to the read data transmitted through the GIO line for inverting and amplifying the read data to provide inverted and amplified data. This data output apparatus can enable a high rate data transmission by decreasing a swing width of data transmitted via the GIO line and also reduce a coupling noise on adjacent lines.

Abstract translation: 全局输入和输出（GIO）线中的数据输出装置和方法经由GIO线传送数据。 该数据输出装置包括读取驱动器，该读取驱动器响应于用于反相和放大数据的读取数据的输入，以将反相和放大的数据输出到GIO线上;响应终止信号驱动的GIO终端单元，用于上升或下降电压电平 在读取驱动器将数据驱动到GIO线之前，将GIO线上的GIO线和响应于通过GIO线传输的读取数据驱动的接收器进行反相和放大，以提供反相和放大数据 。 该数据输出装置可以通过减小通过GIO线传输的数据的摆幅来实现高速率数据传输，并且还减少相邻线路上的耦合噪声。

公开(公告)号：US08981841B2

公开(公告)日：2015-03-17

申请号：US13236970

申请日：2011-09-20

Applicant: Jae-Bum Ko ,  Jong-Chern Lee ,  Sang-Jin Byeon

Inventor： Jae-Bum Ko ,  Jong-Chern Lee ,  Sang-Jin Byeon

IPC: H01L25/00 ,  G11C8/12

CPC classification number: G11C8/12

Abstract: A semiconductor integrated circuit includes a plurality of semiconductor chips respectively selected in response to a plurality of chip selection signals, and a chip selection signal generator configured to generate the chip selection signals in response to one first control signal for deciding whether to drive the semiconductor chips and at least one second control signal for selecting at least one semiconductor chip from among the semiconductor chips.

Abstract translation: 半导体集成电路包括分别响应于多个芯片选择信号选择的多个半导体芯片，以及芯片选择信号发生器，被配置为响应于用于决定是否驱动半导体芯片的一个第一控制信号产生芯片选择信号 以及用于从半导体芯片中选择至少一个半导体芯片的至少一个第二控制信号。

公开(公告)号：US08547764B2

公开(公告)日：2013-10-01

申请号：US12647196

申请日：2009-12-24

Applicant: Jae-Woong Yun ,  Jong-Chern Lee ,  Hee-Jin Byun

Inventor： Jae-Woong Yun ,  Jong-Chern Lee ,  Hee-Jin Byun

IPC: G11C7/00

CPC classification number: G11C29/40 ,  G11C2029/2602

Abstract: A semiconductor memory device includes a plurality of data transmission lines, a plurality of parallel-to-serial conversion sections configured to receive, serially align, and output data from at least two of the plurality of data transmission lines, a plurality of data compression circuits configured to receive, compress, and output outputs of at least two of the plurality of parallel-to-serial conversion sections, and a plurality of data output circuits configured to output respective compression results of the plurality of data compression circuits to an outside of a chip.

Abstract translation: 半导体存储器件包括多个数据传输线，多个并行到串行转换部分，被配置为从所述多个数据传输线中的至少两个数据传输线接收串行对准和输出数据;多个数据压缩电路 被配置为接收，压缩和输出多个并行到串行转换部分中的至少两个的输出，以及多个数据输出电路，被配置为将多个数据压缩电路的各个压缩结果输出到 芯片。

公开(公告)号：US08487431B2

公开(公告)日：2013-07-16

申请号：US12833436

申请日：2010-07-09

Applicant: Sin-Hyun Jin ,  Jong-Chern Lee

Inventor： Sin-Hyun Jin ,  Jong-Chern Lee

IPC: H01L23/48

CPC classification number: H01L23/481 ,  H01L25/0657 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06541

Abstract: A semiconductor integrated circuit having a multi-chip structure includes a plurality of stacked semiconductor chips. At least one of the semiconductor chips includes first and second metal layers separately formed inside the semiconductor chip, a first internal circuit coupled in series between the first and second metal layers inside the semiconductor chip, a first metal path vertically formed over the second metal layer to a first side of the semiconductor chip, and a first through silicon via formed through the semiconductor chip from a second side of the semiconductor chip to the first metal layer.

Abstract translation: 具有多芯片结构的半导体集成电路包括多个层叠的半导体芯片。 半导体芯片中的至少一个包括分开形成在半导体芯片内部的第一和第二金属层，串联耦合在半导体芯片内的第一和第二金属层之间的第一内部电路，垂直形成在第二金属层上的第一金属路径 到半导体芯片的第一侧，以及通过半导体芯片从半导体芯片的第二侧形成到第一金属层的第一贯穿硅通孔。

公开(公告)号：US20130009285A1

公开(公告)日：2013-01-10

申请号：US13620404

申请日：2012-09-14

Applicant: Jun-Gi Choi ,  Jong-Chern Lee

Inventor： Jun-Gi Choi ,  Jong-Chern Lee

IPC: H01L23/544

CPC classification number: H01L22/32 ,  H01L22/34 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor wafer includes at least one chip formed on a substrate, and a scribe line region surrounding the chip. The chip includes a device formation region, and a chip boundary region surrounding the device formation region and formed between the device formation region and the scribe line region. The chip boundary region includes a guard ring structure which physically separates the device formation region from the scribe line region. The guard ring structure includes a signal transfer element which transfers an electric signal between the device formation region and the scribe line region.

Abstract translation: 半导体晶片包括形成在基板上的至少一个芯片和围绕芯片的划线区域。 芯片包括器件形成区域和围绕器件形成区域并形成在器件形成区域和划线区域之间的芯片边界区域。 芯片边界区域包括将器件形成区域与划线区域物理分离的保护环结构。 保护环结构包括在器件形成区域和划线区域之间传送电信号的信号传输元件。

公开(公告)号：US20120154006A1

公开(公告)日：2012-06-21

申请号：US13048185

申请日：2011-03-15

Applicant: Seung-Joon AHN ,  Jong-Chern Lee

Inventor： Seung-Joon AHN ,  Jong-Chern Lee

IPC: H03K3/017

CPC classification number: H03K5/1565

Abstract: A duty cycle correction circuit includes a duty cycle control unit configured to generate a corrected clock signal by correcting a duty cycle of an input clock signal in response to a control signal, a duty cycle detection unit configured to detect a duty cycle of the corrected clock signal and output a detection signal, and a control signal generation unit configured to generate the control signal in response to the detection signal.

Abstract translation: 占空比校正电路包括占空比控制单元，其被配置为通过响应于控制信号校正输入时钟信号的占空比来产生校正时钟信号;占空比检测单元，被配置为检测校正时钟的占空比 信号并输出​​检测信号，以及控制信号生成单元，被配置为响应于检测信号而产生控制信号。

公开(公告)号：US20120008433A1

公开(公告)日：2012-01-12

申请号：US12875803

申请日：2010-09-03

Applicant: Hyun-Su YOON ,  Jong-Chern Lee ,  Seung-Joon Ahn

Inventor： Hyun-Su YOON ,  Jong-Chern Lee ,  Seung-Joon Ahn

IPC: G11C7/00

CPC classification number: G11C7/22 ,  G11C7/222 ,  G11C2207/2272

Abstract: A semiconductor memory device includes an open-loop-type delay locked loop (DLL) configured to generate a clock signal locked by reflecting a first delay amount which actually occurs in a data path and a second delay amount which is required for locking the clock signal, a latency control unit configured to shift an inputted command according to a latency code value corresponding to the first delay amount and latency information, and output the shifted command, and an additional delay line configured to delay the shifted command according to a delay code value corresponding to the second delay amount, and output the command of which operation timing is controlled.

Abstract translation: 半导体存储器件包括开环型延迟锁定环（DLL），其被配置为通过反映实际发生在数据路径中的第一延迟量和锁定时钟信号所需的第二延迟量来产生锁定的时钟信号 等待时间控制单元，被配置为根据与第一延迟量和等待时间信息相对应的等待时间码值来移位输入的命令，并输出移位的命令;以及附加延迟线，被配置为根据延迟代码值来延迟移位的命令 对应于第二延迟量，并且输出控制哪个操作定时的命令。

公开(公告)号：US20110292740A1

公开(公告)日：2011-12-01

申请号：US12949143

申请日：2010-11-18

Applicant: Hee-Jin Byun ,  Jong-Chern Lee

Inventor： Hee-Jin Byun ,  Jong-Chern Lee

IPC: G11C7/10

CPC classification number: G11C7/1006 ,  G11C7/1012 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1093

Abstract: A semiconductor device includes a data alignment unit configured to align serial input data in response to a data strobe signal, a data latching unit configured to latch an output signal of the data alignment unit in response to first and second synchronization pulse signals which are activated according to BL information during a write operation, and a data output unit configured to output an output signal of the data latching unit to a plurality of global data lines in response to a data input strobe signal corresponding to the BL information.

Abstract translation: 半导体器件包括：数据对准单元，被配置为响应于数据选通信号对准串行输入数据;数据锁存单元，被配置为根据第一和第二同步脉冲信号来锁存数据对准单元的输出信号，所述第一和第二同步脉冲信号根据 到写入操作期间的BL信息，以及数据输出单元，被配置为响应于与BL信息对应的数据输入选通信号，将数据锁存单元的输出信号输出到多个全局数据线。