公开(公告)号：US4625162A

公开(公告)日：1986-11-25

申请号：US663806

申请日：1984-10-22

申请人： Robert J. Bosnyak

发明人： Robert J. Bosnyak

IPC分类号： G01R31/02 ,  G11C29/02 ,  G06F11/00 ,  G11C29/00

CPC分类号： G11C29/02

摘要： Circuitry is provided for testing fusible link arrays for short circuits around the fusible links. The resistance of each corresponding link in each of the four quandrants in the array is compared with the resistance of an array of reference fusible links to detect the presence or absence of a short circuit.

摘要翻译： 提供电路用于测试易熔链路周围短路的易熔链路阵列。 将阵列中的每个四个量子中的每个相应链路的电阻与参考可熔链路阵列的电阻进行比较，以检测短路的存在或不存在。

公开(公告)号：US4595875A

公开(公告)日：1986-06-17

申请号：US564642

申请日：1983-12-22

申请人： Albert Chan ,  Mark Fitzpatrick ,  Don Goddard ,  Robert J. Bosnyak ,  Cyrus Tsui

发明人： Albert Chan ,  Mark Fitzpatrick ,  Don Goddard ,  Robert J. Bosnyak ,  Cyrus Tsui

IPC分类号： G11C17/08 ,  G11C29/00 ,  G11C29/02 ,  G11C29/04 ,  G11C29/50 ,  G01R15/12

CPC分类号： G11C29/025 ,  G11C29/02 ,  G11C29/50 ,  G11C17/14 ,  G11C2029/5006

摘要： Test circuitry is included in a PROM memory for detecting shorts between bit lines and word lines and shorts or leaks in a memory cell. The circuitry enables a selected positive voltage to be applied across all memory cells in the memory so that the existance of leaky memory cells or shorts in the memory can be detected during testing. The test circuitry has no appreciable effect on the memory during normal operation of the memory.

摘要翻译： 测试电路包括在PROM存储器中，用于检测位线和字线之间的短路以及存储器单元中的短路或泄漏。 该电路使得所选的正电压可以施加在存储器中的所有存储单元上，使得在测试期间可以检测到存储器中的存储器中存在泄漏的存储器单元或短路。 测试电路在存储器的正常操作期间对存储器没有明显的影响。

公开(公告)号：US07212138B1

公开(公告)日：2007-05-01

申请号：US11325984

申请日：2006-01-05

申请人： Robert J. Bosnyak

发明人： Robert J. Bosnyak

IPC分类号： H03M1/10

CPC分类号： H03M1/502

摘要： An analog-to-digital converter generates and adjusts a digital signal based on a delay caused by an analog signal. The analog signal controls a delay of a first delay chain, and the digital signal controls a delay of a second delay chain. Dependent on a comparison of an output of the first delay chain and an output of the second delay chain, circuitry of the analog-to-digital converter adjusts the digital signal.

摘要翻译： 模数转换器根据由模拟信号引起的延迟产生和调整数字信号。 模拟信号控制第一延迟链的延迟，并且数字信号控制第二延迟链的延迟。 取决于第一延迟链的输出与第二延迟链的输出的比较，模数转换器的电路调整数字信号。

公开(公告)号：US06972596B1

公开(公告)日：2005-12-06

申请号：US10772106

申请日：2004-02-03

申请人： Robert Proebsting ,  Robert J. Bosnyak

发明人： Robert Proebsting ,  Robert J. Bosnyak

IPC分类号： H03K5/003 ,  H03K19/094

CPC分类号： H03K5/003 ,  H01L2225/06527

摘要： One embodiment of the present invention provides a system that amplifies capacitively coupled inter-chip communication signals. During operation, the system transmits a signal through a capacitive transmitter pad and receives a corresponding input signal through a capacitive receiver pad. The system amplifies the input signal by feeding it through a number of cascaded CMOS inverters operating from ever-increasing power supply voltages from the first to the last inverter. The system periodically initializes the input voltage of the first CMOS inverter by: suspending data transmission on the capacitive transmitter pad and setting the voltage on the capacitive transmitter pad to a middle point between a voltage that represents logic “1” and a voltage that represents logic “0”, coupling the output of the first CMOS inverter to its input through a switch, and, after the input voltage of the first CMOS inverter stage substantially stabilizes at the switching threshold, uncoupling the output of the first CMOS inverter stage from the input of the first CMOS inverter stage and then resuming data transmission on the capacitive transmitter pad.

摘要翻译： 本发明的一个实施例提供一种放大电容耦合芯片间通信信号的系统。 在操作期间，系统通过电容式发射器焊盘发送信号，并通过电容式接收器接收相应的输入信号。 该系统通过馈送多个级联的CMOS反相器来放大输入信号，这些反相器从第一个到最后一个逆变器的不断增加的电源电压工作。 系统通过以下方式周期性地初始化第一CMOS反相器的输入电压：将数据传输暂停在电容式发射器焊盘上，并将电容式发射器焊盘上的电压设置为表示逻辑“1”的电压与表示逻辑“1”的电压之间的中间点 “0”，通过开关将第一CMOS反相器的输出耦合到其输入，并且在第一CMOS反相器级的输入电压基本上稳定在开关阈值之后，将第一CMOS反相器级的输出与输入 的第一个CMOS反相器级，然后在电容式发射器焊盘上恢复数据传输。

公开(公告)号：US06396308B1

公开(公告)日：2002-05-28

申请号：US09795281

申请日：2001-02-27

申请人： Robert J. Bosnyak ,  Robert J. Drost

发明人： Robert J. Bosnyak ,  Robert J. Drost

IPC分类号： H03F345

CPC分类号： G11C7/065 ,  G11C2207/005

摘要： A sense amplifier having dual differential inputs configured to accept differential analog input voltages. The differential analog input voltages are fused to determine a weighted signal digitally representative of the differential analog input voltages. An input offset voltage cancellation circuit may be coupled to the sense amplifier to reduce an input offset voltage of the sense amplifier.

摘要翻译： 具有双差分输入的读出放大器被配置为接受差分模拟输入电压。 差分模拟输入电压被融合以确定数字代表差分模拟输入电压的加权信号。 输入偏移电压消除电路可以耦合到读出放大器以减小读出放大器的输入偏移电压。

公开(公告)号：US06313659B1

公开(公告)日：2001-11-06

申请号：US09667473

申请日：2000-12-27

申请人： Robert J. Bosnyak ,  Jose M. Cruz ,  Robert L. Drost

发明人： Robert J. Bosnyak ,  Jose M. Cruz ,  Robert L. Drost

IPC分类号： H03K1716

CPC分类号： H03K19/0005

摘要： A CMOS impedance matching circuit includes an amplifier and a feedback circuit. The amplifier allows control of the impedance by controlling the V/I characteristic. The amplifier is sized to provide the desired impedance. The feedback circuit clamps the maximum excursions of the input signal, thereby maximizing signal speed. It also provides a higher impedance to noise beyond the dead band. In one embodiment of the present invention, the amplifier includes an amplifier circuit in parallel with an amplifier buffer. The amplifier buffer provides no gain and simply performs the inverting function when no gain is required for impedance matching. In one embodiment, the amplifier circuit includes a plurality of switchable amplifiers coupled in parallel with each other. Each of the switchable amplifiers has a different gain, and the one with the right amount of gain for the needed impedance matching is chosen using control inputs. Each of the switchable amplifiers is preferably constructed using pull up and pull down circuits, which ensure that the voltage is within the compliance range of the remote driver circuit. In the absence of an input, the feedback circuit biases the transmission line to the trigger level of the remote receiver circuit, ensuring a quick response when an input is received.

摘要翻译： CMOS阻抗匹配电路包括放大器和反馈电路。 该放大器允许通过控制V / I特性来控制阻抗。 放大器的大小可以提供所需的阻抗。 反馈电路钳位输入信号的最大偏移，从而使信号速度最大化。 它还为死区之外的噪声提供更高的阻抗。 在本发明的一个实施例中，放大器包括与放大器缓冲器并联的放大器电路。 当阻抗匹配不需要增益时，放大器缓冲器不提供增益，只需执行反相功能即可。 在一个实施例中，放大器电路包括彼此并联耦合的多个可切换放大器。 每个可切换放大器具有不同的增益，并且使用控制输入来选择具有所需阻抗匹配的正确增益量的增益。 每个可切换放大器优选地使用上拉和下拉电路构成，其确保电压在远程驱动器电路的合规范围内。 在没有输入的情况下，反馈电路将传输线偏置到远程接收器电路的触发电平，确保在接收到输入时的快速响应。

公开(公告)号：US6084452A

公开(公告)日：2000-07-04

申请号：US107898

申请日：1998-06-30

申请人： Robert J. Drost ,  Jose M. Cruz ,  Robert J. Bosnyak

发明人： Robert J. Drost ,  Jose M. Cruz ,  Robert J. Bosnyak

IPC分类号： H03K5/156 ,  H03K3/017

CPC分类号： H03K5/1565

摘要： An apparatus adjusts the duty cycle of a single-ended clock signal. The single-ended clock signal oscillates between first and second voltages. The apparatus includes an error indication circuit, a duty cycle error measurement circuit and a duty cycle adjuster. The error indication circuit includes a reference circuit and a comparison circuit. The reference circuit is coupled to a first node having the first voltage and a second node having the second voltage to generate a reference signal from the first and second voltages. The reference circuit includes at least one instance of a first electrical characteristic cell. The comparison circuit is coupled to receive a feedback clock signal and to generate a comparison signal therefrom. The comparison circuit includes at least one instance of the first electrical characteristic cell. The duty cycle error measurement circuit is coupled to receive the reference signal and the comparison signal. The duty cycle error measurement circuit rejects the common mode of the reference and comparison signals and passes the differential mode of the reference and comparison signals to generate a duty cycle adjust signal responsive to receiving the reference and comparison signals. The duty cycle adjuster is coupled to receive an input clock signal and the duty cycle adjust signal and to provide the single-ended clock signal. The single-ended clock signal has a duty cycle determined at least in part by the duty cycle adjust signal.

摘要翻译： 一个装置调整单端时钟信号的占空比。 单端时钟信号在第一和第二电压之间振荡。 该装置包括误差指示电路，占空比误差测量电路和占空比调节器。 误差指示电路包括参考电路和比较电路。 参考电路耦合到具有第一电压的第一节点和具有第二电压的第二节点以从第一和第二电压产生参考信号。 参考电路包括第一电特征单元的至少一个实例。 比较电路被耦合以接收反馈时钟信号并从其产生比较信号。 比较电路包括第一电特征单元的至少一个实例。 负载周期误差测量电路被耦合以接收参考信号和比较信号。 占空比误差测量电路拒绝参考和比较信号的共模，并通过参考和比较信号的差分模式，以响应于接收参考和比较信号产生占空比调整信号。 负载周期调节器被耦合以接收输入时钟信号和占空比调整信号并提供单端时钟信号。 单端时钟信号具有至少部分由占空比调整信号确定的占空比。

公开(公告)号：US6020765A

公开(公告)日：2000-02-01

申请号：US866653

申请日：1997-05-30

申请人： Robert J. Drost ,  Robert J. Bosnyak

发明人： Robert J. Drost ,  Robert J. Bosnyak

IPC分类号： H03K5/26 ,  H03L7/085 ,  H03L7/087 ,  H04L7/033 ,  H04L25/40 ,  H03D13/00

CPC分类号： H03L7/085 ,  H04L7/033

摘要： A frequency difference detector includes a pulse generator that receives an NRZ signal and a reference signal and provides data pulses having first edges based on edges of the NRZ signal and second edges based on edges of the reference signal, a pulse router that routes consecutive ones of the data pulses to different signal paths, a voltage generator that receives the data pulses from the signal paths and provides voltage signals with amplitudes based on pulse widths of the data pulses, and a comparison circuit that receives the voltage signals and provides error pulses with amplitudes based on voltage differences between the voltage signals. The amplitudes of the error pulses represent a frequency difference between the NRZ signal and the reference signal. Preferably, the data pulses have leading edges based on edges of the NRZ signal and the lagging edges based on leading edges of the reference signal immediately following the edges of the NRZ signal. It is also preferred that the error pulses have a repetition rate that corresponds to the edges of the NRZ signal, a current amplitude that is proportional to the frequency difference between the NRZ signal and the reference signal, and a polarity that represents a sign of the frequency difference between the NRZ signal and the reference signal. The frequency difference detector is well-suited for use in a frequency/phase-locked loop that provides a clock recovery circuit.

摘要翻译： 频率差检测器包括脉冲发生器，其接收NRZ信号和参考信号，并且基于参考信号的边缘提供基于NRZ信号和第二边缘的第一边缘的数据脉冲，脉冲路由器将连续的 数据脉冲到不同的信号路径，电压发生器，其从信号路径接收数据脉冲，并提供基于数据脉冲的脉冲宽度的幅度的电压信号;以及比较电路，其接收电压信号并提供具有幅度的误差脉冲 基于电压信号之间的电压差。 误差脉冲的振幅表示NRZ信号和参考信号之间的频率差。 优选地，数据脉冲具有基于NRZ信号的边缘的前沿，并且基于紧跟NRZ信号的边缘的参考信号的前沿之后的滞后边缘。 还优选地，误差脉冲具有对应于NRZ信号的边缘的重复率，与NRZ信号和参考信号之间的频率差成比例的电流幅度，以及表示该NRZ信号的符号的极性 NRZ信号与参考信号之间的频率差。 频率差检测器非常适用于提供时钟恢复电路的频率/锁相环。

公开(公告)号：US6016082A

公开(公告)日：2000-01-18

申请号：US23360

申请日：1998-02-13

申请人： Jose M. Cruz ,  Robert J. Bosnyak ,  Robert J. Drost

发明人： Jose M. Cruz ,  Robert J. Bosnyak ,  Robert J. Drost

IPC分类号： H03B1/00 ,  H03B5/12 ,  H03L7/093 ,  H03L7/099 ,  H03L7/183 ,  H03B5/18

CPC分类号： H03L7/183 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1271 ,  H03L7/093 ,  H03L7/099 ,  H03B2201/0208

摘要： A microprocessor includes an on-chip low phase noise CMOS LC capacitance oscillator. The LC oscillator is relatively insensitive to power supply fluctuations. In addition, the LC oscillator is operable over a range of frequencies sufficient to support both normal full power operation, and reduced power operation of the microprocessor. The LC oscillator minimizes clock jitter problems and so permits extension of the microprocessor operating frequency to even higher levels than heretofore were possible. An output signal from a phase-frequency detector is a frequency control signal on a frequency control input line of a level converter and filter circuit of the LC oscillator. The output signal from level converter and filter circuit is a filtered frequency control signal on a control voltage input line to a continuously modifiable gigahertz frequency voltage controlled oscillator (VCO) circuit. Continuously modifiable gigahertz frequency VCO circuit generates an output signal with a frequency that is dependent on the voltage on control voltage input line. The output signal from the continuously modifiable gigahertz frequency VCO is a differential current signal to a level shifter output circuit. The level shifter output circuit converts the current signal to a single-ended voltage that is supplied to an output driver. The output driver provides the output signal to a clock distribution network.

摘要翻译： 微处理器包括片上低相位噪声CMOS LC电容振荡器。 LC振荡器对电源波动相对不敏​​感。 此外，LC振荡器可以在足以支持正常全功率操作和微处理器的功率操作的减少的频率范围内操作。 LC振荡器使时钟抖动问题最小化，因此允许将微处理器工作频率扩展到甚至比以前更高的水平。 来自相位频率检测器的输出信号是LC振荡器的电平转换器和滤波器电路的频率控制输入线上的频率控制信号。 来自电平转换器和滤波器电路的输出信号是在可连续修改的千兆赫兹频率压控振荡器（VCO）电路的控制电压输入线上的滤波频率控制信号。 连续可修改的千兆赫兹频率VCO电路产生的输出信号的频率取决于控制电压输入线上的电压。 来自连续可修改的千兆赫兹频率VCO的输出信号是到电平移位器输出电路的差分电流信号。 电平移位器输出电路将电流信号转换为提供给输出驱动器的单端电压。 输出驱动器将输出信号提供给时钟分配网络。

公开(公告)号：US5920215A

公开(公告)日：1999-07-06

申请号：US885048

申请日：1997-06-30

申请人： Robert J. Drost ,  Robert J. Bosnyak

发明人： Robert J. Drost ,  Robert J. Bosnyak

IPC分类号： H03L7/089 ,  H03L7/06

CPC分类号： H03L7/0896

摘要： In a charge pump the noise due to switching transients on the input pulse lines is kept to extremely low levels by translating input up/down pulses into small signal differential pulses which swing a differential pair of transistors by a small amount. This is done with level converters. The differential pair is kept in a saturation region, so that a large swing is not needed from the level converters and channel creation/destruction noise is avoided in addition to the noise reduction due to smaller swings. To avoid inherent offsets which might require a nonzero delta time width difference in the input pulses to produce a zero delta current, identical differential structures are used at the inputs for the two input pulse signals.

摘要翻译： 在电荷泵中，通过将输入上/下脉冲转换成将差分晶体管对摆动少量的小信号差分脉冲，将输入脉冲线上的切换瞬变引起的噪声保持在极低的水平。 这是用电平转换器完成的。 差分对保持在饱和区域，使得除了由于较小的摆动引起的噪声降低之外，电平转换器不需要大的摆幅并且避免了信道产生/破坏噪声。 为了避免可能需要输入脉冲中的非零增量时间宽度差产生零增量电流的固有偏移，在两个输入脉冲信号的输入端使用相同的差分结构。