公开(公告)号：US11683053B2

公开(公告)日：2023-06-20

申请号：US17178604

申请日：2021-02-18

Applicant: KIOXIA CORPORATION

Inventor： Riki Suzuki ,  Toshikatsu Hida ,  Osamu Torii ,  Hiroshi Yao ,  Kiyotaka Iwasaki

IPC: H03M13/00 ,  H03M13/35 ,  G06F11/10 ,  H03M13/29 ,  G06F3/06 ,  G11C29/52 ,  G11C7/10 ,  G11B20/18 ,  G11C29/04

CPC classification number: H03M13/35 ,  G06F3/064 ,  G06F3/0619 ,  G06F3/0653 ,  G06F3/0679 ,  G06F11/1008 ,  G06F11/1044 ,  G06F11/1048 ,  G06F11/1068 ,  G06F11/1076 ,  G11C29/52 ,  H03M13/29 ,  H03M13/2906 ,  H03M13/2957 ,  G11B20/1833 ,  G11C7/1006 ,  G11C2029/0411

Abstract: According to one embodiment, a nonvolatile memory includes a plurality of memory areas and controller circuit including an error correction code encoder. The error correction code encoder encodes a first data to generate a first parity in a first operation and encodes a second data to generate a second parity in a second operation. The controller circuit writes the first data and the first parity into a first memory area among the plurality of memory areas and writes the second data and the second parity into a second memory area among the plurality of memory areas. The size of the second data is smaller than the size of the first data and the size of the second parity is equal to the size of the first parity.

公开(公告)号：US11562792B2

公开(公告)日：2023-01-24

申请号：US17184991

申请日：2021-02-25

Applicant: KIOXIA CORPORATION

Inventor： Riki Suzuki ,  Yoshihisa Kojima

IPC: G11C16/10 ,  G11C16/26 ,  G11C16/08 ,  G11C29/44 ,  G11C16/22 ,  G11C7/10 ,  G11C29/42 ,  G11C16/30

Abstract: A memory system includes a non-volatile memory having a plurality of memory cells and a controller. The controller is configured to switch a mode for controlling an access operation to the non-volatile memory from a first mode to a second mode, in response to receiving from a host, a first command for instructing the controller to switch the mode from the first mode to the second mode. The access operation controlled according to the second mode improves data retention relative to the access operation controlled according to the first mode.

公开(公告)号：US11416169B2

公开(公告)日：2022-08-16

申请号：US17199586

申请日：2021-03-12

Applicant: Kioxia Corporation

Inventor： Yoshihisa Kojima ,  Riki Suzuki

IPC: G06F3/00 ,  G06F3/06 ,  G06F12/06

Abstract: A memory system includes a controller that transmits, to a memory chip, one first command set indicating a head of a third storage area being one of second storage areas, in a case where first data is read to a first buffer of the memory chip. The first data includes a plurality of first data segments having been stored in the second storage areas. The memory chip includes circuitry that outputs a second data segment and a third data segment to the controller in a period after the controller transmits the first command set to the memory chip before the controller transmits a second command set to the memory chip. The second data segment is a data segment having been stored in the third storage area. The third data segment is a data segment having been stored in a fourth storage area different from the third storage area.