公开(公告)号：US12073890B2

公开(公告)日：2024-08-27

申请号：US18174916

申请日：2023-02-27

Applicant: KIOXIA CORPORATION

Inventor： Masanobu Shirakawa ,  Tsukasa Tokutomi ,  Marie Takada

IPC: G11C16/26 ,  G11C11/56 ,  G11C16/04 ,  H10B43/27 ,  H10B43/35

CPC classification number: G11C16/26 ,  G11C11/5671 ,  G11C16/0483 ,  H10B43/27 ,  H10B43/35

Abstract: According to one embodiment, a memory system includes a semiconductor memory device and a controller. The device includes a plurality of memory cells capable of storing at least first to third data and a word line coupled to the plurality of memory cells. The first data is determined by a first read operation including a first read level. The second data is determined by a second read operation including a second read level. The third data is determined by a third read operation including a third read level. The controller controls the semiconductor memory device to perform a forth read operation including the first and second read levels in a search operation for first to third read voltages corresponding to the first to third read levels, respectively.

公开(公告)号：US11699499B2

公开(公告)日：2023-07-11

申请号：US17187705

申请日：2021-02-26

Applicant: KIOXIA CORPORATION

Inventor： Tsukasa Tokutomi ,  Kiwamu Watanabe ,  Riki Suzuki ,  Toshikatsu Hida ,  Takahiro Onagi

IPC: G11C29/42 ,  G11C29/24 ,  G11C29/44 ,  G11C29/12

CPC classification number: G11C29/42 ,  G11C29/24 ,  G11C29/44 ,  G11C2029/1202

Abstract: According to one embodiment, a memory system includes a memory controller and a nonvolatile memory with multiple planes each provided with multiple word lines, memory cell groups, dummy word lines, and dummy memory cell groups. The memory controller writes data to a memory cell group connected to a corresponding word line of any of the planes, such that a plane to which k-th data are to be written is different from a plane to which (k+m−1)-th data are to be written, and writes the parities to any of the dummy memory cell groups. The combinations of the data used for generating the different parities are different from each other.

公开(公告)号：US11561736B2

公开(公告)日：2023-01-24

申请号：US17370535

申请日：2021-07-08

Applicant: KIOXIA CORPORATION

Inventor： Marie Takada ,  Masanobu Shirakawa ,  Tsukasa Tokutomi

IPC: G11C29/00 ,  G06F3/06 ,  G11C16/26 ,  G11C16/10 ,  G11C16/16 ,  G11C16/08 ,  G06F11/10 ,  G11C29/52 ,  G11C16/04 ,  G11C11/56 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11556 ,  H01L27/11582

Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The memory system is capable of executing a first operation and a second operation. In the first operation, the controller issues a first command sequence, the semiconductor memory applies a first voltage to a first word line and applies a second voltage to a second word line to read data from the first memory, and the read data is transmitted to the controller from the semiconductor memory. In the second operation, the controller issues a second command sequence, the semiconductor memory applies a third voltage to the first word line and applies a fourth voltage to the second word line, and data held in the memory cell array is left untransmitted to the controller.