公开(公告)号：US11211138B2

公开(公告)日：2021-12-28

申请号：US17003937

申请日：2020-08-26

Applicant: KIOXIA CORPORATION

Inventor： Tsukasa Tokutomi ,  Kiwamu Watanabe ,  Yuko Noda

IPC: G11C29/50 ,  G11C29/42 ,  G11C29/44 ,  G11C16/08 ,  G11C16/30 ,  G11C16/10 ,  G11C16/26

Abstract: A memory system includes a memory chip and a memory controller. The memory chip has a first plane and a second plane. A threshold voltage corresponding to multiple bit data is set for each of the memory cells. The memory controller causes the memory chip to execute a first read process on the first plane and the second plane in parallel by using a plurality of first read voltages different from each other for the first plane and the second plane. The first read process being a process of reading a data group of one bit among the multiple bits by using the first read voltages. The memory controller subsequently adjusts the voltage levels of the first read voltages on the basis of the data group read from the memory cells of the first plane and the data group read from the memory cells of the second plane.

公开(公告)号：US12300328B2

公开(公告)日：2025-05-13

申请号：US18177877

申请日：2023-03-03

Applicant: Kioxia Corporation

Inventor： Masahiro Saito ,  Kiwamu Watanabe ,  Yuko Noda ,  Tsukasa Tokutomi ,  Yoshiki Takai

IPC: G11C7/00 ,  G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26

Abstract: A memory controller receives first, second, and third data by first, second, and third reads, specifying a first address, and respectively specifying first, second, and third read voltages higher in this order. The controller instructs a memory to execute a fourth read specifying a fourth read voltage lower than the first read voltage and the first address when a first difference between a first-value-bit count of the first data and an expected value is smaller than a second difference between a first-value-bit count of the third data and the expected value. The memory controller instructs the memory to execute a fifth read specifying a fifth read voltage higher than the third read voltage and the first address when the first difference is larger than the second difference.

公开(公告)号：US11756642B2

公开(公告)日：2023-09-12

申请号：US17476229

申请日：2021-09-15

Applicant: Kioxia Corporation

Inventor： Tsukasa Tokutomi ,  Masanobu Shirakawa ,  Kiwamu Watanabe ,  Kengo Kurose

IPC: G11C29/12 ,  G11C16/26 ,  G11C16/08 ,  G06F3/06

CPC classification number: G11C29/12 ,  G06F3/0619 ,  G06F3/0658 ,  G06F3/0673 ,  G11C16/08 ,  G11C16/26 ,  G11C2029/1202

Abstract: A memory system according to an embodiment includes a semiconductor memory, and a memory controller. The semiconductor memory comprises memory cells and word lines. Each of the word lines is connected to the memory cells. The memory controller executes a patrol operation including a read operation of the semiconductor memory. The word lines are classified into one of first and second groups. The memory controller executes patrol operations in which the word lines are respectively selected in a first patrol period and, in a second patrol period subsequent to the first patrol period, executes a patrol operation in which the word line included in the first group is selected and omits a patrol operation in which the word line included in the second group is selected.

公开(公告)号：US12283330B2

公开(公告)日：2025-04-22

申请号：US18354300

申请日：2023-07-18

Applicant: KIOXIA CORPORATION

Inventor： Tsukasa Tokutomi ,  Masanobu Shirakawa ,  Kiwamu Watanabe ,  Kengo Kurose

IPC: G11C29/12 ,  G06F3/06 ,  G11C16/08 ,  G11C16/26

Abstract: A memory system according to an embodiment includes a semiconductor memory, and a memory controller. The semiconductor memory comprises memory cells and word lines. Each of the word lines is connected to the memory cells. The memory controller executes a patrol operation including a read operation of the semiconductor memory. The word lines are classified into one of first and second groups. The memory controller executes patrol operations in which the word lines are respectively selected in a first patrol period and, in a second patrol period subsequent to the first patrol period, executes a patrol operation in which the word line included in the first group is selected and omits a patrol operation in which the word line included in the second group is selected.

公开(公告)号：US11699499B2

公开(公告)日：2023-07-11

申请号：US17187705

申请日：2021-02-26

Applicant: KIOXIA CORPORATION

Inventor： Tsukasa Tokutomi ,  Kiwamu Watanabe ,  Riki Suzuki ,  Toshikatsu Hida ,  Takahiro Onagi

IPC: G11C29/42 ,  G11C29/24 ,  G11C29/44 ,  G11C29/12

CPC classification number: G11C29/42 ,  G11C29/24 ,  G11C29/44 ,  G11C2029/1202

Abstract: According to one embodiment, a memory system includes a memory controller and a nonvolatile memory with multiple planes each provided with multiple word lines, memory cell groups, dummy word lines, and dummy memory cell groups. The memory controller writes data to a memory cell group connected to a corresponding word line of any of the planes, such that a plane to which k-th data are to be written is different from a plane to which (k+m−1)-th data are to be written, and writes the parities to any of the dummy memory cell groups. The combinations of the data used for generating the different parities are different from each other.