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    Semiconductor device for generating constant potential
    21.
    发明授权
    Semiconductor device for generating constant potential 失效

    公开(公告)号：US5319256A

    公开(公告)日：1994-06-07

    申请号：US875301

    申请日：1992-04-29

    申请人： Masaru Koyanagi ,  Tsuyoshi Etoh

    发明人： Masaru Koyanagi ,  Tsuyoshi Etoh

    IPC分类号： G11C11/413 ,  G05F3/24 ,  G11C7/12 ,  G11C16/06 ,  G11C17/00 ,  G11C17/18 ,  H03K3/01 ,  H03K3/26

    CPC分类号： G05F3/24 ,  G11C7/12

    摘要： A constant potential generating semiconductor device includes: an output circuit having a first channel type first transistor and a second channel type second transistor serially connected between a first power source and a second power source V.sub.ss, a connection point between the first and second transistors being connected to an output terminal; a reference potential generating circuit having a first current limiter, a first channel type third transistor, a second channel type fourth transistor, and a second current limiter serially connected between a first power source and a fourth power source, a first connection point interconnecting the first current limiter and the third transistor being connected to the gate of the first transistor, a second connection point interconnecting the fourth transistor and the second current limiter being connected to the gate of the second transistor, the first connection point being connected to the gate of the third transistor, and the gate of the fourth transistor being connected to the second connection point; an output mode switching circuit having a fifth transistor and a sixth transistor, the fifth transistor interconnecting the gate of the first transistor and a fifth power source at a fourth connection point, the sixth transistor interconnecting the gate of the second transistor and a sixth power source at a fifth connection point, the output mode switching circuit having a switching input terminal, a switching signal for switching an output mode being applied to the switching mode input terminal, the switching input terminal being connected to the gates of the fifth and sixth transistors, during a first output mode with a first level signal being applied to the switching input terminal, both the fifth and sixth transistors turning off to maintain the connection between the gates of the first and second transistors and the first and second connection points, respectively, and during a second output mode with a second level signal being applied to the switching input terminal, both the fifth and sixth transistors turning on to electrically disconnect the gates of the first and second transistors from the first and second connection points, respectively; and a potential difference suppressing circuit for suppressing a potential difference between the gate and back gate of the fourth transistor during the second output mode.

    Semiconductor integrated circuit having substrate potential detecting circuit commonly used
    22.
    发明授权
    Semiconductor integrated circuit having substrate potential detecting circuit commonly used 失效
    具有常用基板电位检测电路的半导体集成电路

    公开(公告)号：US5057704A

    公开(公告)日：1991-10-15

    申请号：US496961

    申请日：1990-03-21

    申请人： Masaru Koyanagi ,  Minoru Yamada

    发明人： Masaru Koyanagi ,  Minoru Yamada

    IPC分类号： H01L27/04 ,  G05F3/20 ,  G11C11/407 ,  H01L21/822 ,  H03K19/094

    CPC分类号： G05F3/205

    摘要： A semiconductor integrated circuit for controlling the substrate potential is disclosed, in which a substrate potential generating circuit is connected to a substrate and can be operated on at least a certain operation voltage level to generate the substrate potential. A detection circuit outputs a first detection signal upon detecting that the substrate potential has become lower than the operation voltage level by more than a preset amount, and outputs a second signal upon detecting that the substrate potential has reached a preset level which is slightly lower than the operation voltage level. A charging circuit charges the substrate upon receiving the first detection signal and interrupts the operation of charging the substrate upon receiving the second detection signal.

    Semiconductor integrated circuit
    23.
    发明授权
    Semiconductor integrated circuit 有权
    半导体集成电路

    公开(公告)号：US08258817B2

    公开(公告)日：2012-09-04

    申请号：US12884623

    申请日：2010-09-17

    申请人： Ryo Fukuda ,  Masaru Koyanagi

    发明人： Ryo Fukuda ,  Masaru Koyanagi

    IPC分类号： H03K5/153

    CPC分类号： H01L27/092 ,  H01L2924/0002 ,  H03F3/3028 ,  H03F3/45183 ,  H03F2200/411 ,  H03F2203/45511 ,  H01L2924/00

    摘要： According to one embodiment, a semiconductor integrated circuit includes first to six transistors and a constant current source circuit. The first and second transistors form a current mirror circuit connected to a first power source node. The third and fourth transistors form a differential pair circuit. The third and fourth transistors receive first and second external signals at their gates, respectively. The constant current source circuit has one end connected to source terminals of the third and fourth transistors, and the other end connected to a second power source node. The fifth and sixth transistors form a current pathway between a common gate node of the first and second transistors and the constant current source circuit. The gate of fifth transistor is connected to a signal output node. The gate of sixth transistor receives a signal of logic opposite to a signal to be obtained at the signal output node.

    摘要翻译： 根据一个实施例，半导体集成电路包括第一至六个晶体管和恒流源电路。 第一和第二晶体管形成连接到第一电源节点的电流镜电路。 第三和第四晶体管形成差分对电路。 第三和第四晶体管分别在其栅极处接收第一和第二外部信号。 恒流源电路的一端连接到第三和第四晶体管的源极端子，另一端连接到第二电源节点。 第五和第六晶体管在第一和第二晶体管的公共栅极节点与恒流源电路之间形成电流通路。 第五晶体管的栅极连接到信号输出节点。 第六晶体管的栅极接收与在信号输出节点处获得的信号相反的逻辑信号。

    OUTPUT BUFFER CIRCUIT, INPUT BUFFER CIRCUIT, AND INPUT/OUTPUT BUFFER CIRCUIT
    24.
    发明申请
    OUTPUT BUFFER CIRCUIT, INPUT BUFFER CIRCUIT, AND INPUT/OUTPUT BUFFER CIRCUIT 有权
    输出缓冲电路，输入缓冲电路和输入/输出缓冲电路

    公开(公告)号：US20110133791A1

    公开(公告)日：2011-06-09

    申请号：US12963114

    申请日：2010-12-08

    申请人： Masaru Koyanagi ,  Yasufumi Kajiyama ,  Ryo Fukuda ,  Fumiyoshi Matsuoka ,  Yasuhiro Suematsu

    发明人： Masaru Koyanagi ,  Yasufumi Kajiyama ,  Ryo Fukuda ,  Fumiyoshi Matsuoka ,  Yasuhiro Suematsu

    IPC分类号： H03K3/01

    CPC分类号： H03K19/00384 ,  H03K19/01721

    摘要： An output buffer circuit in accordance with an embodiment comprises a plurality of buffer circuits, each of the buffer circuits including a transistor operative to change an output signal of an output terminal in response to a change in an input signal, the output buffer circuit being configured to enable the plurality of buffer circuits to be driven selectively. Each of the plurality of buffer circuits includes a plurality of output transistors having respective current paths formed in parallel to one another between a fixed voltage terminal supplying a certain fixed voltage and an output terminal, and being selectively rendered in an operable state in accordance with a control signal provided from external. The plurality of output transistors included in each of the plurality of buffer circuits are formed having a certain size ratio.

    摘要翻译： 根据实施例的输出缓冲器电路包括多个缓冲电路，每个缓冲电路包括一个晶体管，用于响应于输入信号的变化而改变输出端的输出信号，该输出缓冲电路被配置 以使得能够选择性地驱动多个缓冲电路。 多个缓冲电路中的每一个包括多个输出晶体管，其具有在提供一定固定电压的固定电压端子和输出端子之间彼此并联形成的各自的电流路径，并且根据 控制信号由外部提供。 包含在多个缓冲电路的每一个中的多个输出晶体管形成为具有一定的尺寸比。

    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE
    25.
    发明申请
    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
    非易失性半导体存储器件

    公开(公告)号：US20100309733A1

    公开(公告)日：2010-12-09

    申请号：US12793062

    申请日：2010-06-03

    申请人： Katsumi Abe ,  Masahiro Yoshihara ,  Masaru Koyanagi

    发明人： Katsumi Abe ,  Masahiro Yoshihara ,  Masaru Koyanagi

    IPC分类号： G11C7/10 ,  G11C7/00

    CPC分类号： G11C7/1078 ,  G11C7/1084 ,  G11C16/04 ,  G11C16/20 ,  G11C29/02 ,  G11C29/028 ,  G11C2207/2254

    摘要： A nonvolatile semiconductor memory device is provided, which includes an input buffer provided with a first inverter that can electrically adjust circuit threshold values, a circuit: threshold value monitor provided with a second inverter having the same circuit configuration as the first inverter to detect the circuit threshold values of the first inverter when the input and output of the second inverter are short-circuited, respectively, a memory storing parameter values that correspond to the circuit threshold values detected by the circuit threshold value monitor, and a data-reader circuit reading the parameter values given to the first inverter from the memory.

    摘要翻译： 提供了一种非易失性半导体存储器件，其包括：输入缓冲器，其具有能够电调节电路阈值的第一反相器;电路：具有与第一反相器相同电路结构的第二反相器的阈值监视器，用于检测电路 分别在第二反相器的输入和输出短路时第一反相器的阈值，存储与由电路阈值监视器检测的电路阈值对应的参数值的存储器，读取数据读取器电路的数据读取器电路 从存储器给予第一反相器的参数值。

    Semiconductor memory
    28.
    发明授权
    Semiconductor memory 失效
    半导体存储器

    公开(公告)号：US07206242B2

    公开(公告)日：2007-04-17

    申请号：US11013688

    申请日：2004-12-17

    申请人： Katsuki Matsudera ,  Kazuhide Yoneya ,  Masaru Koyanagi

    发明人： Katsuki Matsudera ,  Kazuhide Yoneya ,  Masaru Koyanagi

    IPC分类号： G11C7/00

    CPC分类号： G11C7/1066 ,  G11C7/1006 ,  G11C7/1051 ,  G11C2207/107

    摘要： A semiconductor memory includes a converter configured to convert each read-data of plural bits read from a memory core into serial data, respectively, in synchronization with a read clock to generate converted read-data. An output register holds the converted read-data in synchronization with the read clock. A selector selects one bit from each plural bits of the converted read-data, in accordance with a control data, and to supply the selected bit to the output register.

    摘要翻译： 半导体存储器包括：转换器，被配置为与读取时钟同步地分别将从存储器芯读取的多个位的每个读取数据转换为串行数据，以产生转换的读取数据。 输出寄存器与读取时钟同步地保存转换的读取数据。 选择器根据控制数据从转换的读取数据的每个多个比特中选择一个比特，并将所选择的比特提供给输出寄存器。

    MOS-type semiconductor integrated circuit
    29.
    发明授权
    MOS-type semiconductor integrated circuit 失效

    公开(公告)号：US06700411B2

    公开(公告)日：2004-03-02

    申请号：US10234106

    申请日：2002-09-05

    申请人： Katsuki Matsudera ,  Masaru Koyanagi

    发明人： Katsuki Matsudera ,  Masaru Koyanagi

    IPC分类号： H03K19094

    CPC分类号： H03K19/0963 ,  H03K19/00315

    摘要： An MOS-type semiconductor integrated circuit has two MOS transistors of the opposite conductivity channel types connected in series between a high-voltage potential terminal and a ground potential terminal. Those two MOS transistors constitute an inverter and their gates are connected together to an input node. As output nodes, first and second nodes are provided with a current path in between which includes transistors whose gates are connected to the high-voltage potential terminal. A current path including the first transistor which constitutes a switch is inserted between the first node and the output node, and a current path including the second transistor and a barrier transistor is inserted between the second node and the output node. The gates of the first and second transistors are respectively connected with complementary clock signals. The bate of the barrier transistor is connected to the high-voltage potential terminal.

    Semiconductor integrated circuit having output buffer
    30.
    发明授权
    Semiconductor integrated circuit having output buffer 失效

    公开(公告)号：US06563351B2

    公开(公告)日：2003-05-13

    申请号：US09965951

    申请日：2001-09-27

    申请人： Tadashi Onizawa ,  Natsuki Kushiyama ,  Masaru Koyanagi ,  Katsuki Matsudera

    发明人： Tadashi Onizawa ,  Natsuki Kushiyama ,  Masaru Koyanagi ,  Katsuki Matsudera

    IPC分类号： H03B100

    CPC分类号： H03K19/01707 ,  H03K17/102 ,  H03K17/162

    摘要： A semiconductor integrated circuit includes first and second MOS transistors and a capacitor. The first MOS transistor has a drain connected to an output terminal, a gate and a source. The second MOS transistor has a gate, a drain connected to the source of the first MOS transistor and a source and has the same conductivity type as the first MOS transistor. The capacitor has one electrode connected to the gate of the first MOS transistor and the other electrode connected to a node whose potential changes in a complementary fashion with respect to the drain potential of the first MOS transistor and functions to cancel out an influence, caused by the coupling of a mirror capacitor which exists between the gate and drain of the first MOS transistor, affecting the gate potential of the first MOS transistor.