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31 条记录 (耗时 0.028 秒)

    Method and apparatus for reducing power consumption of a processing integrated circuit
    21.
    发明授权
    Method and apparatus for reducing power consumption of a processing integrated circuit 失效
    用于降低处理集成电路的功耗的方法和装置

    公开(公告)号：US06834353B2

    公开(公告)日：2004-12-21

    申请号：US09682816

    申请日：2001-10-22

    申请人： Jack Robert Smith ,  Sebastian Theodore Ventrone

    发明人： Jack Robert Smith ,  Sebastian Theodore Ventrone

    IPC分类号： G06F132

    CPC分类号： G06F1/3203

    摘要： In a first aspect, a method is provided for conserving power in a processing integrated circuit. The method includes the steps of (1) calculating power consumption for executing an instruction and data corresponding to the instruction; and (2) executing the instruction if such execution does not exceed a predetermined power level. In a second aspect, a method is provided for conserving power in a processing integrated circuit employing a plurality of execution units. The method includes the steps of (1) comparing a total power to be consumed by the processing integrated circuit to a power budget for the processing integrated circuit; and (2) if the total power exceeds the power budget, freezing execution of an instruction by one of the plurality of execution units so as to allow execution of the instruction to continue at a later time from where execution was frozen. Numerous other aspects are provided, as are systems and apparatus.

    摘要翻译： 在第一方面，提供了一种用于在处理集成电路中节省功率的方法。 该方法包括以下步骤：（1）计算用于执行指令的功耗和对应于该指令的数据; 和（2）如果这样的执行不超过预定功率电平，则执行指令。 在第二方面，提供一种用于在采用多个执行单元的处理集成电路中节省功率的方法。 该方法包括以下步骤：（1）将由处理集成电路消耗的总功率与处理集成电路的功率预算进行比较; 以及（2）如果总功率超过功率预算，则冻结多个执行单元之一的指令的执行，以便允许执行指令在执行被冻结的较后时间继续。 还提供了许多其他方面，系统和装置也是如此。

    Self regulating temperature/performance/voltage scheme for micros (X86)
    22.
    发明授权
    Self regulating temperature/performance/voltage scheme for micros (X86) 有权
    微调自适应温度/性能/电压方案（X86）

    公开(公告)号：US6119241A

    公开(公告)日：2000-09-12

    申请号：US183342

    申请日：1998-10-30

    申请人： Michel Salib Michail ,  Wilbur David Pricer ,  Sebastian Theodore Ventrone

    发明人： Michel Salib Michail ,  Wilbur David Pricer ,  Sebastian Theodore Ventrone

    IPC分类号： G06F1/08 ,  G06F1/20 ,  G06F1/32 ,  G06F1/26

    CPC分类号： G06F1/324 ,  G06F1/206 ,  G06F1/3203 ,  G06F1/3296 ,  Y02B60/1217 ,  Y02B60/1285

    摘要： A processor which optimizes performance opportunistically by using a hierarchy of variables comprising voltage, clocking and the operations being performed by the processor or its system. The invention accomplishes performance optimization by defining various states with the goal that the processor stays in an optimal performance state of accelerated voltage and clock when the processor executional units are operating. The states are selected by a logic network based on information that is provided by temperature sensors and a performance control. The logic network can be envisioned as an UP-DOWN counter. The counter can be advanced UP or DOWN the state "ladder" as the conditions warrant.

    摘要翻译： 一种处理器，通过使用包括电压，时钟和由处理器或其系统执行的操作的变量的层次来机会地优化性能。 本发明通过定义各种状态来实现性能优化，目的在于处理器执行单元正在运行时处理器处于加速电压和时钟的最佳性能状态。 状态由逻辑网络基于由温度传感器和性能控制提供的信息来选择。 逻辑网络可以设想为一个UP-DOWN计数器。 根据条件，计数器可以向上或向下进入状态“梯子”。

    Structures including circuits for noise reduction in digital systems
    23.
    发明授权
    Structures including circuits for noise reduction in digital systems 有权
    包括数字系统降噪电路的结构

    公开(公告)号：US08037337B2

    公开(公告)日：2011-10-11

    申请号：US11946096

    申请日：2007-11-28

    申请人： Nancy H. Pratt ,  Sebastian Theodore Ventrone

    发明人： Nancy H. Pratt ,  Sebastian Theodore Ventrone

    IPC分类号： G06F1/04

    CPC分类号： G06F1/06 ,  G06F1/08 ,  G06F9/3869

    摘要： A design structure including a digital system. The digital system includes (a) a first logic circuit and a second logic circuit, (b) a first register, (c) a second register, (d) a third register, (e) a clock generator circuit, and (f) a controller circuit. The first logic circuit is capable of obtaining first data and sending second data. The second logic circuit is capable of obtaining the second data and sending third data. The clock generator circuit is capable of asserting (i) a first register clock signal at a first time point, (ii) a second register clock signal at a second time point, and (iii) a third register clock signal at a third time point. The controller circuit is capable of (i) determining a fourth time point, (ii) determining a fifth time point, (iii) controlling the clock generator circuit to assert the second register clock signal.

    摘要翻译： 包括数字系统的设计结构。 数字系统包括（a）第一逻辑电路和第二逻辑电路，（b）第一寄存器，（c）第二寄存器，（d）第三寄存器，（e）时钟发生器电路，以及（f） 一个控制器电路。 第一逻辑电路能够获得第一数据并发送第二数据。 第二逻辑电路能够获得第二数据并发送第三数据。 时钟发生器电路能够在第一时间点断言（i）第一寄存器时钟信号，（ii）在第二时间点的第二寄存器时钟信号，以及（iii）第三时间点的第三寄存器时钟信号 。 控制器电路能够（i）确定第四时间点，（ii）确定第五时间点，（iii）控制时钟发生器电路以断言第二寄存器时钟信号。

    Noise reduction in digital systems
    25.
    发明授权
    Noise reduction in digital systems 失效
    数字系统降噪

    公开(公告)号：US07317348B2

    公开(公告)日：2008-01-08

    申请号：US11275773

    申请日：2006-01-27

    申请人： Nancy H. Pratt ,  Sebastian Theodore Ventrone

    发明人： Nancy H. Pratt ,  Sebastian Theodore Ventrone

    IPC分类号： H03K5/00

    CPC分类号： G06F1/04 ,  H03K5/1504 ,  H03K19/00361

    摘要： A digital system and a method for operating the same. The digital system includes (a) a first logic circuit and a second logic circuit, (b) a first register, (c) a second register, (d) a third register, (e) a clock generator circuit, and (f) a controller circuit. The first logic circuit is capable of obtaining first data and sending second data. The second logic circuit is capable of obtaining the second data and sending third data. The clock generator circuit is capable of asserting (i) a first register clock signal at a first time point, (ii) a second register clock signal at a second time point, and (iii) a third register clock signal at a third time point. The controller circuit is capable of (i) determining a fourth time point, (ii) determining a fifth time point, (iii) controlling the clock generator circuit to assert the second register clock signal.

    摘要翻译： 数字系统及其操作方法。 数字系统包括（a）第一逻辑电路和第二逻辑电路，（b）第一寄存器，（c）第二寄存器，（d）第三寄存器，（e）时钟发生器电路，以及（f） 一个控制器电路。 第一逻辑电路能够获得第一数据并发送第二数据。 第二逻辑电路能够获得第二数据并发送第三数据。 时钟发生器电路能够在第一时间点断言（i）第一寄存器时钟信号，（ii）在第二时间点的第二寄存器时钟信号，以及（iii）第三时间点的第三寄存器时钟信号 。 控制器电路能够（i）确定第四时间点，（ii）确定第五时间点，（iii）控制时钟发生器电路以断言第二寄存器时钟信号。

    Auto-linking of function logic state with testcase regression list
    28.
    发明授权
    Auto-linking of function logic state with testcase regression list 失效
    功能逻辑状态与测试案例回归列表的自动链接

    公开(公告)号：US06934656B2

    公开(公告)日：2005-08-23

    申请号：US10605884

    申请日：2003-11-04

    申请人： Jason Michael Norman ,  Nancy H. Pratt ,  Sebastian Theodore Ventrone

    发明人： Jason Michael Norman ,  Nancy H. Pratt ,  Sebastian Theodore Ventrone

    IPC分类号： G01R31/14 ,  G06F11/26

    CPC分类号： G06F11/261

    摘要： A method and system for identifying logic function areas, which make up a virtual machine, that are affected by specific testcases. A Hardware Descriptor Language (HDL) is used to create a software model of the virtual machine. A simulator compiles and analyzes the HDL model, and creates a matrix scoreboard identifying logic function areas in the virtual machine. A complete list of testcases is run on the virtual machine while a monitor correlates each testcase with affected logic function areas to fill in the matrix scoreboard. When a subsequent test failure occurs, either because of a modification to a logic function area, or the execution of a new test, all logic function areas that are affected, either directly or indirectly, are identified.

    摘要翻译： 用于识别构成虚拟机的逻辑功能区域受到特定测试用例影响的方法和系统。 硬件描述符语言（HDL）用于创建虚拟机的软件模型。 模拟器编译和分析HDL模型，并创建一个标识虚拟机中逻辑功能区域的矩阵记分板。 测试用例的完整列表在虚拟机上运行，​​而监视器将每个测试用例与受影响的逻辑功能区域相关联，以填充矩阵记分板。 当随后的测试失败发生时，由于对逻辑功能区域的修改或新测试的执行，所有被直接或间接影响的逻辑功能区域都被识别。

    High level automatic core configuration
    30.
    发明授权
    High level automatic core configuration 有权
    高级自动核心配置

    公开(公告)号：US06425109B1

    公开(公告)日：2002-07-23

    申请号：US09360384

    申请日：1999-07-23

    申请人： Charles N. Choukalos ,  Alvar Antonio Dean ,  Scott Alan Tetreault ,  Sebastian Theodore Ventrone

    发明人： Charles N. Choukalos ,  Alvar Antonio Dean ,  Scott Alan Tetreault ,  Sebastian Theodore Ventrone

    IPC分类号： G06F1750

    CPC分类号： G06F17/5045

    摘要： A system and method for interconnecting a plurality of cores into a single functional core. The method involves creating for each core a pin configuration structure based on a set of configuration rules. When the cores to be interconnected are selected, the pin configuration structure is accessed by the configurator program tool of the present invention. The configurator program tool then connects the cores together using the pin configuration structure and configuration rules for the selected cores. The configurator program tool generates an error-free high level model of the interconnected cores. The configurator program tool allows configuration flexibility and is general enough to handle most configuration scenarios. The tool is also easy to code, extensible, and can be applied to existing core designs with no modification of the cores themselves.

    摘要翻译： 一种用于将多个核心互连成单个功能核心的系统和方法。 该方法包括基于一组配置规则为每个核心创建引脚配置结构。 当选择要互连的芯时，通过本发明的配置程序工具访问引脚配置结构。 然后，配置程序工具使用所选核心的引脚配置结构和配置规则将内核连接在一起。 配置程序工具生成互连核心的无错误高级模型。 配置程序工具允许配置灵活性，并且足以处理大多数配置场景。 该工具也易于编码，可扩展，并且可以应用于现有的核心设计，而不改变内核本身。