公开(公告)号：US6025273A

公开(公告)日：2000-02-15

申请号：US55433

申请日：1998-04-06

申请人： Chao-Cheng Chen ,  Chia-Shiung Tsai ,  Hun-Jan Tao

发明人： Chao-Cheng Chen ,  Chia-Shiung Tsai ,  Hun-Jan Tao

IPC分类号： H01L21/033 ,  H01L21/311 ,  H01L21/768 ,  H01L23/522 ,  H01L21/283

CPC分类号： H01L21/31144 ,  H01L21/76816 ,  H01L23/5226 ,  H01L21/0332 ,  H01L21/31116 ,  H01L2924/0002

摘要： A method is achieved for fabricating small contact holes in an interlevel dielectric (ILD) layer for integrated circuits. The method increases the ILD etch rate while reducing residue build-up on the contact hole sidewall. This provides a very desirable process for making contact holes small than 0.25 um in width. After depositing the ILD layer over the partially completed integrated circuit which includes patterned doped first polysilicon layers, a second polysilicon layer is deposited and doped with carbon by ion implantation. A photoresist mask is used to etch openings in the carbon doped polysilicon layer to form a hard mask. The photoresist is removed, and the contact holes are plasma etched in the ILD layer while free carbon released from the hard mask, during etching, reduces the free oxygen in the plasma. This results in an enhanced fluorine (F.sup.+) etch rate for the contact holes in the ILD layer and reduces the residue build-up on the sidewalls of the contact holes. The hard mask is anneal in O.sub.2 to form an oxide layer and any surface carbon is removed in a wet etch. Reliable metal plugs can now be formed by depositing a barrier layer, such as titanium (Ti) or titanium nitride (TiN) and a metal such as tungsten (W) and etching back or chemical/mechanical polishing back to the oxide layer.

摘要翻译： 实现了用于在用于集成电路的层间电介质（ILD）层中制造小接触孔的方法。 该方法增加了ILD蚀刻速率，同时减少了接触孔侧壁上的残留物积聚。 这提供了使接触孔宽度小于0.25μm的非常理想的方法。 在包括图案化掺杂的第一多晶硅层的部分完成的集成电路上沉积ILD层之后，通过离子注入沉积第二多晶硅层并掺杂碳。 光致抗蚀剂掩模用于蚀刻碳掺杂多晶硅层中的开口以形成硬掩模。 去除光致抗蚀剂，并且在ILD层中对接触孔进行等离子体蚀刻，而在蚀刻期间从硬掩模释放出的游离碳降低了等离子体中的游离氧。 这导致ILD层中的接触孔的氟（F +）蚀刻速率增加，并减少了接触孔的侧壁上的残留物积聚。 硬掩模在O 2中退火以形成氧化物层，并且在湿蚀刻中除去任何表面碳。 现在可以通过沉积诸如钛（Ti）或氮化钛（TiN）和诸如钨（W）的金属的阻挡层并且将氧化物层回蚀刻或化学/机械抛光来形成可靠的金属插塞。

公开(公告)号：US5981398A

公开(公告)日：1999-11-09

申请号：US58122

申请日：1998-04-10

申请人： Chia-Shiung Tsai ,  Chao-Cheng Chen ,  Hun-Jan Tao

发明人： Chia-Shiung Tsai ,  Chao-Cheng Chen ,  Hun-Jan Tao

IPC分类号： H01L21/3213 ,  H01L21/3065

CPC分类号： H01L21/32136 ,  H01L21/32137 ,  H01L21/32139

摘要： A method for forming a chlorine containing plasma etched patterned layer. There is first provided a substrate 10 employed within a microelectronics fabrication. There is then formed over the substrate a blanket target layer 12 formed of a material susceptible to etching within a second plasma employing a chlorine containing etchant gas composition. There is then formed upon the blanket target a blanket hard mask layer 14 formed of a material selected from the group consisting of silsesquioxane spin-on-glass (SOG) materials and amorphous carbon materials. There is then formed upon the blanket hard mask layer a patterned photoresist layer 16. There is then etched while employing the patterned photoresist layer as a first etch mask layer and while employing a first plasma employing a fluorine containing etchant gas composition the blanket hard mask layer to form a patterned hard mask layer. Finally, there is then etched while employing at least the patterned hard mask layer as a second etch mask layer and while employing the second plasma employing the chlorine containing etchant gas composition the blanket target layer to form the patterned target layer.

摘要翻译： 一种形成含氯等离子体蚀刻图案层的方法。 首先提供了在微电子制造中使用的衬底10。 然后在衬底上形成由使用含氯蚀刻剂气体组合物在第二等离子体内易于蚀刻的材料形成的覆盖层目标层12。 然后在橡皮布目标上形成由选自倍半硅氧烷旋涂玻璃（SOG）材料和无定形碳材料的材料形成的橡皮布硬掩模层14。 然后在橡皮布硬掩模层上形成图案化的光致抗蚀剂层16.然后在使用图案化的光致抗蚀剂层作为第一蚀刻掩模层的同时进行蚀刻，并且在使用含氟蚀刻剂气体组合物的第一等离子体的同时， 以形成图案化的硬掩模层。 最后，在使用至少图案化的硬掩模层作为第二蚀刻掩模层的同时蚀刻，并且在使用含氯蚀刻剂气体组合物的第二等离子体时，覆盖目标层以形成图案化目标层。

公开(公告)号：US5925575A

公开(公告)日：1999-07-20

申请号：US940002

申请日：1997-09-29

申请人： Hun-Jan Tao ,  Chia-Shiung Tsai

发明人： Hun-Jan Tao ,  Chia-Shiung Tsai

IPC分类号： H01L21/3105 ,  H01L21/762 ,  H01L21/00

CPC分类号： H01L21/31056 ,  H01L21/76224

摘要： A process for forming a planarized, insulator, or silicon oxide filled shallow trench has been developed. The process features a hybrid planarization procedure, comprised of an initial dry etching cycle, used to remove all but about 100 to 500 Angstroms of silicon oxide, from subsequent device regions, or regions outside the insulator filled trench. Silicon oxide residing on the insulator filled trench is protected by a photoresist shape. A final chemical mechanical polishing procedure is than employed to remove both the silicon oxide, on the insulator filled shallow trench, as well as removing the remaining silicon oxide on silicon nitride, in subsequent device regions. An endpoint monitoring procedure allows the detection of the remaining 100 to 500 Angstroms of silicon oxide, on silicon nitride. This allows the procedure to be terminated at this stage, thus avoiding gouging or trenching phenomena of insulator in the shallow trench, which can occur due to misalignment of the masking photoresist shape to the underlying insulator filled trench.

摘要翻译： 已经开发了用于形成平坦化，绝缘体或氧化硅填充的浅沟槽的工艺。 该方法具有混合平面化方法，其包括初始干蚀刻循环，用于从后续器件区域或绝缘体填充沟槽外部的区域除去所有但约100至500埃的氧化硅。 位于绝缘体填充沟槽上的硅氧化物被光致抗蚀剂形状保护。 最后的化学机械抛光方法不仅用于除去在绝缘体填充的浅沟槽上的氧化硅，以及在随后的器件区域中去除氮化硅上剩余的氧化硅。 端点监测程序允许在氮化硅上检测剩余的100至500埃的氧化硅。 这允许在该阶段终止该过程，从而避免由于掩模光致抗蚀剂形状与下面的绝缘体填充的沟槽的未对准而在浅沟槽中产生的凹陷或挖沟现象。

公开(公告)号：US5904566A

公开(公告)日：1999-05-18

申请号：US868842

申请日：1997-06-09

申请人： Hun-Jan Tao ,  Chia-Shiung Tsai

发明人： Hun-Jan Tao ,  Chia-Shiung Tsai

IPC分类号： H01L21/311 ,  H01L21/46

CPC分类号： H01L21/31116

摘要： A method for forming a via through a nitrogenated silicon oxide layer. There is first provided a substrate. There is then formed over the substrate a nitrogenated silicon oxide layer. There is then formed upon the nitrogenated silicon oxide layer a patterned photoresist layer. Finally, there is then etched the nitrogenated silicon oxide layer through a reactive ion etch (RIE) plasma etch method while employing the patterned photoresist layer as a patterned photoresist etch mask layer to form a via through the nitrogenated silicon oxide layer. The reactive ion etch (RIE) method employs an etchant gas composition comprising: (1) a perfluorocarbon having a carbon:fluorine atomic ratio at least about 1:3; (2) oxygen; and (3) argon.

摘要翻译： 一种通过氮化氧化硅层形成通孔的方法。 首先提供基板。 然后在衬底上形成氮化氧化硅层。 然后在氮化氧化硅层上形成图案化的光致抗蚀剂层。 最后，然后通过反应离子蚀刻（RIE）等离子体蚀刻方法蚀刻氮化氧化硅层，同时使用图案化的光致抗蚀剂层作为图案化的光致抗蚀剂蚀刻掩模层，以形成通过氮化氧化硅层的通孔。 反应离子蚀刻（RIE）方法采用蚀刻剂气体组合物，其包括：（1）碳氟原子比至少约1:3的全氟化碳; （2）氧气; 和（3）氩气。

公开(公告)号：US5837599A

公开(公告)日：1998-11-17

申请号：US695006

申请日：1996-08-09

申请人： Hun-Jan Tao ,  Chia-Shiung Tsai

发明人： Hun-Jan Tao ,  Chia-Shiung Tsai

IPC分类号： H01L21/683 ,  H01L21/20

CPC分类号： H01L21/6831 ,  Y10S438/928

摘要： A method of improving electrostatic chucking efficiency between a silicon wafer which has an oxide layer formed on a back side and a susceptor positioned in a wafer processing chamber wherein the back side is opposite to the side of the wafer to be processed for integrated circuit devices including the steps of first forming an electrically conducting layer on top of the oxide layer by transforming to a more hydrophilic oxide structure and then positioning the wafer on the susceptor with the electrically conducting layer contacting the susceptor.

摘要翻译： 一种提高在背面形成有氧化层的硅晶片与位于晶片处理室中的基座之间的静电夹持效率的方法，其中背面与用于集成电路器件的待处理晶片侧相反， 首先通过转变为更亲水的氧化物结构，然后将晶片定位在基座上，使导电层与基座接触，首先在氧化物层的顶部上形成导电层的步骤。

公开(公告)号：US06399515B1

公开(公告)日：2002-06-04

申请号：US09336809

申请日：1999-06-21

申请人： Hun-Jan Tao ,  Chia-Shiung Tsai

发明人： Hun-Jan Tao ,  Chia-Shiung Tsai

IPC分类号： H01L21302

CPC分类号： H01L21/28123 ,  H01L21/32137

摘要： A method for forming a patterned silicon containing layer. There is first provided a substrate. There is then formed over the substrate a blanket silicon containing layer. There is then formed over the blanket silicon containing layer a patterned photoresist layer. There is then etched, while employing a first plasma etch method in conjunction with the patterned photoresist layer as a first etch mask layer, the blanket silicon containing layer to form a partially etched blanket silicon containing layer. The first plasma etch method employs a first etchant gas composition comprising an etchant gas which upon plasma activation forms an active fluorine containing etchant species. There is then etched, while employing a second plasma etch method in conjunction with the patterned photoresist layer as a second etch mask layer the partially etched blanket silicon containing layer to form a fully patterned silicon containing layer. The second plasma etch method employs a second etchant gas composition which upon plasma activation forms an active halogen containing etchant species other than an active fluorine containing etchant species. The present invention also contemplates an embodiment which incorporates a blanket hard mask layer formed interposed between the blanket silicon containing layer and the patterned photoresist layer. The present invention may be employed for forming gate electrodes within field effect transistors (FETs).

摘要翻译： 一种形成图案化含硅层的方法。 首先提供基板。 然后在衬底上形成覆盖有硅的层。 然后在覆盖硅含硅层上形成图案化的光致抗蚀剂层。 然后蚀刻，同时采用第一等离子体蚀刻方法结合图案化的光致抗蚀剂层作为第一蚀刻掩模层，覆盖硅含硅层以形成部分蚀刻的覆盖硅含硅层。 第一种等离子体蚀刻方法使用包含蚀刻剂气体的第一蚀刻剂气体组合物，其在等离子体激活时形成活性含氟蚀刻剂物质。 然后蚀刻，同时采用第二等离子体蚀刻方法结合图案化的光致抗蚀剂层作为第二蚀刻掩模层，部分蚀刻的覆盖硅含硅层以形成完全图案化的含硅层。 第二等离子体蚀刻方法采用第二蚀刻剂气体组合物，其在等离子体激活时形成除活性含氟蚀刻剂物质之外的含活性卤素的蚀刻剂物质。 本发明还考虑了一种实施例，其包括形成在橡皮布硅含量层和图案化光致抗蚀剂层之间的橡皮布硬掩模层。 本发明可用于在场效应晶体管（FET）内形成栅电极。

公开(公告)号：US06242350B1

公开(公告)日：2001-06-05

申请号：US09270594

申请日：1999-03-18

申请人： Hun-Jan Tao ,  Chia-Shiung Tsai ,  Yuan-Chang Huang

发明人： Hun-Jan Tao ,  Chia-Shiung Tsai ,  Yuan-Chang Huang

IPC分类号： H01L2100

CPC分类号： H01L21/02071 ,  H01L21/31138 ,  H01L21/32137

摘要： A method for removing residual photoresist and polymer residues from silicon wafers after a polysilicon plasma etch with minimal gate oxide loss is described. The method is particularly useful for cleaning wafers after polysilicon or polycide gate etching in MOSFET with when very thin gate oxides (

摘要翻译： 描述了在具有最小的栅极氧化物损耗的多晶硅等离子体蚀刻之后从硅晶片去除残留的光致抗蚀剂和聚合物残余物的方法。 该方法对于在具有非常薄的栅极氧化物（<100）的MOSFET中的多晶硅或多晶硅栅极蚀刻之后清洁晶片特别有用。 为了蚀刻多晶硅栅极结构的最终部分，包括过蚀刻以去除隔离的多晶硅斑块，使用含有HBr的蚀刻剂来提供高多晶硅至栅极氧化物选择性。 该蚀刻部件使得在光致抗蚀剂的表面上形成聚合物面纱，除了水性蚀刻剂之外难以除去，这也会引起严重的栅极氧化物损失。 本发明的方法通过全干式蚀刻工艺解决了面纱聚合物，光致抗蚀剂和侧壁聚合物的去除。 在第一个全干法中，残留物和光致抗蚀剂和侧壁聚合物通过使用O 2 / N 2混合物和单个O 2 /碳氟化合物步骤的步骤顺序在商业ICP等离子体灰化器中除去以除去面纱聚合物。 替代的清洁程序在低基板温度下用O 2 / N 2 / H 2气体混合物除去面纱聚合物，并在较高温度下除去光致抗蚀剂和侧壁聚合物。 通过任一方法的最大栅极氧化物损耗小于10埃。

公开(公告)号：US6043163A

公开(公告)日：2000-03-28

申请号：US999233

申请日：1997-12-29

申请人： Chia-Shiung Tsai ,  Chao-Cheng Chen ,  Hun-Jan Tao

发明人： Chia-Shiung Tsai ,  Chao-Cheng Chen ,  Hun-Jan Tao

IPC分类号： H01L21/3213 ,  H01L21/00 ,  H01L21/3065

CPC分类号： H01L21/32136

摘要： A new method of etching metal lines using HCl in the overetch step to prevent undercutting of the metal lines is described. Semiconductor device structures are provided in and on a semiconductor substrate. The semiconductor device structures are covered with an insulating layer. A barrier metal layer is deposited overlying the insulating layer. A metal layer is deposited overlying the barrier metal layer. A hard mask layer is deposited overlying the metal layer. The hard mask layer is covered with a layer of photoresist which is exposed, developed, and patterned to form the desired photoresist mask. The hard mask layer is etched away where it is not covered by the photoresist mask leaving a patterned hard mask. The metal layer is etched away where it is not covered by the patterned hard mask to form the metal lines. Overetching is performed to remove the barrier layer where it is not covered by the hard mask wherein HCl gas is one of the etchant gases used in the overetching whereby hydrogen ions from the HCl gas react with the metal layer and the barrier metal layer to form a passivation layer on the sidewalls of the metal lines thereby preventing undercutting of the metal lines resulting in metal lines having a vertical profile. The photoresist mask is removed and fabrication of the integrated circuit device is completed.

摘要翻译： 描述了在过蚀刻步骤中使用HCl蚀刻金属线以防止金属线的底切的新方法。 半导体器件结构设置在半导体衬底中和半导体衬底上。 半导体器件结构被绝缘层覆盖。 覆盖在绝缘层上的阻挡金属层被沉积​​。 沉积在阻挡金属层上的金属层。 覆盖金属层的硬掩模层被沉积。 硬掩模层被一层光致抗蚀剂覆盖，该层被曝光，显影和图案化以形成所需的光致抗蚀剂掩模。 将硬掩模层蚀刻掉，其中未被光致抗蚀剂掩模覆盖，留下图案化的硬掩模。 金属层被蚀刻掉，其中未被图案化的硬掩模覆盖以形成金属线。 进行过蚀刻以去除其未被硬掩模覆盖的阻挡层，其中HCl气体是用于过蚀刻中的蚀刻剂气体之一，其中来自HCl气体的氢离子与金属层和阻挡金属层反应形成 钝化层，从而防止金属线的底切，导致具有垂直轮廓的金属线。 去除光致抗蚀剂掩模并完成集成电路器件的制造。

公开(公告)号：US5880005A

公开(公告)日：1999-03-09

申请号：US956967

申请日：1997-10-23

申请人： Chia Shiung Tsai ,  Hun-Jan Tao

发明人： Chia Shiung Tsai ,  Hun-Jan Tao

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76224

摘要： A method for creating a tapered profile insulator shape, on an underlying silicon nitride layer, using a photoresist shape as a mask, has been developed. A two step dry etching procedure is used, featuring a first dry etching phase, using an etching chemistry comprised of argon, CHF.sub.3 and CF.sub.4, resulting in a tapered profile insulator shape, underlying the photoresist shape. A second dry etching phase, exhibiting high etch rate selectivity between insulator layer and underlying silicon nitride, via use of an etching chemistry comprised of argon, CHF.sub.3, CH.sub.2 F.sub.2, and CH.sub.3 F, is used to remove residual insulator layer from the underlying silicon nitride layer, without significant attack of the underlying silicon nitride layer.

摘要翻译： 已经开发了使用光致抗蚀剂形状作为掩模在下面的氮化硅层上形成锥形轮廓绝缘体形状的方法。 使用两步干蚀刻方法，其特征在于使用由氩，CHF 3和CF 4构成的蚀刻化学品的第一干蚀刻阶段，导致在光致抗蚀剂形状下面的锥形轮廓绝缘体形状。 通过使用由氩，CHF 3，CH 2 F 2和CH 3 F组成的蚀刻化学品，在绝缘体层和下面的氮化硅之间表现出高蚀刻速率选择性的第二干法蚀刻阶段用于从下面的氮化硅层去除残留的绝缘体层， 没有显着攻击下面的氮化硅层。

公开(公告)号：US08367563B2

公开(公告)日：2013-02-05

申请号：US12575280

申请日：2009-10-07

申请人： Matt Yeh ,  Hui Ouyang ,  Da-Yuan Lee ,  Kuang Yuan Hsu ,  Hun-Jan Tao ,  Xiong-Fei Yu

发明人： Matt Yeh ,  Hui Ouyang ,  Da-Yuan Lee ,  Kuang Yuan Hsu ,  Hun-Jan Tao ,  Xiong-Fei Yu

IPC分类号： H01L21/3205

CPC分类号： H01L29/401 ,  H01L21/823828 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/66545

摘要： A method for fabricating a semiconductor device is disclosed. In one embodiment, the method may include providing a substrate; forming a gate structure including a first dummy gate over the substrate; removing the first dummy gate from the gate structure to form a trench; forming an interfacial layer, high-k dielectric layer, and capping layer to partially fill in the trench; forming a second dummy gate over the capping layer, wherein the second dummy gate fills the trench; and replacing the second dummy gate with a metal gate. In one embodiment, the method may include providing a substrate; forming an interfacial layer over the substrate; forming a high-k dielectric layer over the interfacial layer; forming an etch stop layer over the high-k dielectric layer; forming a capping layer including a low thermal budget silicon over the etch stop layer; forming a dummy gate layer over the capping layer; forming a gate structure; and performing a gate replacement process.

摘要翻译： 公开了一种制造半导体器件的方法。 在一个实施例中，该方法可以包括提供衬底; 在所述衬底上形成包括第一虚拟栅极的栅极结构; 从栅极结构去除第一伪栅极以形成沟槽; 形成界面层，高k电介质层和覆盖层以部分地填充在沟槽中; 在所述覆盖层上形成第二虚拟栅极，其中所述第二伪栅极填充所述沟槽; 并用金属栅极替换第二虚拟栅极。 在一个实施例中，该方法可以包括提供衬底; 在衬底上形成界面层; 在界面层上形成高k电介质层; 在所述高k电介质层上形成蚀刻停止层; 在所述蚀刻停止层上形成包括低热预算硅的覆盖层; 在覆盖层上形成虚拟栅极层; 形成栅极结构; 并进行门更换处理。