公开(公告)号：US6040248A

公开(公告)日：2000-03-21

申请号：US104032

申请日：1998-06-24

申请人： Chao-Cheng Chen ,  Ming-Hsin Huang ,  Hun-Jan Tao ,  Chia-Shiung Tsai

发明人： Chao-Cheng Chen ,  Ming-Hsin Huang ,  Hun-Jan Tao ,  Chia-Shiung Tsai

IPC分类号： H01L21/311 ,  H01L21/768 ,  H01L21/302 ,  C23F1/02 ,  H01L21/461

CPC分类号： H01L21/31138 ,  H01L21/76802

摘要： A process for plasma etching of contact and via openings in low-k organic polymer dielectric layers is described which overcomes problems of sidewall bowing and hardmask pattern deterioration by etching the organic layer in a high density plasma etcher with a chlorine/inert gas plasma. By adding chlorine to the oxygen/inert gas plasma, the development of an angular aspect or faceting of the hardmask pattern edges by ion bombardment is abated. Essentially vertical sidewalls are obtained in the openings etched in the organic polymer layer while hardmask pattern integrity is maintained. The addition of a passivating agent such as nitrogen, BCl.sub.3, or CHF.sub.3 to the etchant gas mixture further improves the sidewall profile by reducing bowing through protective polymer formation.

摘要翻译： 描述了一种用于等离子体蚀刻低k有机聚合物介电层中的接触和通孔开口的方法，其通过用氯/惰性气体等离子体在高密度等离子体蚀刻机中蚀刻有机层来克服侧壁弯曲和硬掩模图案劣化的问题。 通过向氧/惰性气体等离子体中加入氯，减少了通过离子轰击形成硬掩模图案边缘的角度方面或刻面。 在保持硬掩模图案完整性的同时，在有机聚合物层中蚀刻的开口中获得基本垂直的侧壁。 钝化剂如氮气，BCl3或CHF3添加到蚀刻剂气体混合物中，通过减少通过保护性聚合物形成的弯曲来进一步改善侧壁轮廓。

公开(公告)号：US06194128B1

公开(公告)日：2001-02-27

申请号：US09156053

申请日：1998-09-17

申请人： Hun-Jan Tao ,  Chao-Cheng Chen ,  Chia-Shiung Tsai

发明人： Hun-Jan Tao ,  Chao-Cheng Chen ,  Chia-Shiung Tsai

IPC分类号： G03F700

CPC分类号： H01L21/76835 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/31116 ,  H01L21/3144 ,  H01L21/3145 ,  H01L21/76807 ,  H01L21/76813 ,  H01L21/76814 ,  H01L2221/1036

摘要： A novel method of dual damascene etching is disclosed. It is shown that the performance of ULSI circuits can be improved by shrinking interconnect dimensions through the use of dual damascene processes, using hard-masks to achieve vertical walls and hence smaller spaces in the damascene structures, introducing low-k (dielectric constant) insulating materials to reduce RC delays, and metallizing with copper without the deleterious effects of bridging after CMP. These are accomplished by using a novel recipe for etching the hard-masks used in a dual damascene process and still another recipe for etching low-k dielectric layers in three different combinations with oxide-based dielectric layers.

摘要翻译： 公开了一种双镶嵌蚀刻的新方法。 通过使用双镶嵌工艺，通过使用硬掩模实现垂直壁并因此在镶嵌结构中实现更小的空间来缩小互连尺寸，可以提高ULSI电路的性能，引入低k（介电常数）绝缘 减少RC延迟的材料，以及铜的金属化，而没有CMP后的桥接的有害影响。 这些是通过使用用于蚀刻在双镶嵌工艺中使用的硬掩模的新配方来实现的，还有另一种用于蚀刻具有氧化物基电介质层的三种不同组合的低k电介质层的方案。

公开(公告)号：US6043163A

公开(公告)日：2000-03-28

申请号：US999233

申请日：1997-12-29

申请人： Chia-Shiung Tsai ,  Chao-Cheng Chen ,  Hun-Jan Tao

发明人： Chia-Shiung Tsai ,  Chao-Cheng Chen ,  Hun-Jan Tao

IPC分类号： H01L21/3213 ,  H01L21/00 ,  H01L21/3065

CPC分类号： H01L21/32136

摘要： A new method of etching metal lines using HCl in the overetch step to prevent undercutting of the metal lines is described. Semiconductor device structures are provided in and on a semiconductor substrate. The semiconductor device structures are covered with an insulating layer. A barrier metal layer is deposited overlying the insulating layer. A metal layer is deposited overlying the barrier metal layer. A hard mask layer is deposited overlying the metal layer. The hard mask layer is covered with a layer of photoresist which is exposed, developed, and patterned to form the desired photoresist mask. The hard mask layer is etched away where it is not covered by the photoresist mask leaving a patterned hard mask. The metal layer is etched away where it is not covered by the patterned hard mask to form the metal lines. Overetching is performed to remove the barrier layer where it is not covered by the hard mask wherein HCl gas is one of the etchant gases used in the overetching whereby hydrogen ions from the HCl gas react with the metal layer and the barrier metal layer to form a passivation layer on the sidewalls of the metal lines thereby preventing undercutting of the metal lines resulting in metal lines having a vertical profile. The photoresist mask is removed and fabrication of the integrated circuit device is completed.

摘要翻译： 描述了在过蚀刻步骤中使用HCl蚀刻金属线以防止金属线的底切的新方法。 半导体器件结构设置在半导体衬底中和半导体衬底上。 半导体器件结构被绝缘层覆盖。 覆盖在绝缘层上的阻挡金属层被沉积​​。 沉积在阻挡金属层上的金属层。 覆盖金属层的硬掩模层被沉积。 硬掩模层被一层光致抗蚀剂覆盖，该层被曝光，显影和图案化以形成所需的光致抗蚀剂掩模。 将硬掩模层蚀刻掉，其中未被光致抗蚀剂掩模覆盖，留下图案化的硬掩模。 金属层被蚀刻掉，其中未被图案化的硬掩模覆盖以形成金属线。 进行过蚀刻以去除其未被硬掩模覆盖的阻挡层，其中HCl气体是用于过蚀刻中的蚀刻剂气体之一，其中来自HCl气体的氢离子与金属层和阻挡金属层反应形成 钝化层，从而防止金属线的底切，导致具有垂直轮廓的金属线。 去除光致抗蚀剂掩模并完成集成电路器件的制造。

公开(公告)号：US06319822B1

公开(公告)日：2001-11-20

申请号：US09164999

申请日：1998-10-01

申请人： Chao-Cheng Chen ,  Chia-Shiung Tsai ,  Shau-Lin Shue ,  Hun-Jan Tao

发明人： Chao-Cheng Chen ,  Chia-Shiung Tsai ,  Shau-Lin Shue ,  Hun-Jan Tao

IPC分类号： H01L214763

CPC分类号： H01L21/76831 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/31144 ,  H01L21/76802

摘要： A method for etching of sub-quarter micron openings in insulative layers for contacts and vias is described. The method uses hardmask formed of carbon enriched titanium nitride. The hardmask has a high selectivity for etching contact and via openings in relatively thick insulative layers. The high selectivity requires a relatively thin hardmask which can be readily patterned by thin photoresist masks, making the process highly desirable for DUV photolithography. The hardmask is formed by MOCVD using a metallorganic titanium precursor. By proper selection of the MOCVD deposition conditions, a controlled amount of carbon is incorporated into the TiN film. The carbon is released as the hardmask erodes during plasma etching and participates in the formation of a protective polymer coating along the sidewalls of the opening being etched in the insulative layer. The protective sidewall polymer inhibits lateral chemical etching and results in openings with smooth, straight, and near-vertical sidewalls without loss of dimensional integrity.

摘要翻译： 描述了用于在接触和通孔的绝缘层中蚀刻二分之一微米开口的方法。 该方法使用由富碳氮化钛形成的硬掩模。 硬掩模在相对较厚的绝缘层中对蚀刻接触和通孔的选择性很高。 高选择性需要相对薄的硬掩模，其可以通过薄的光致抗蚀剂掩模容易地图案化，使得该工艺对于DUV光刻非常期望。 硬掩模由MOCVD使用金属有机钛前体形成。 通过适当选择MOCVD沉积条件，将受控量的碳纳入TiN膜中。 在等离子体蚀刻期间，随着硬掩模腐蚀而释放碳，并且参与沿着在绝缘层中蚀刻的开口的侧壁形成保护性聚合物涂层。 保护性侧壁聚合物抑制侧向化学蚀刻并导致具有平滑，直的和近垂直的侧壁的开口，而不损失尺寸完整性。

公开(公告)号：US6025273A

公开(公告)日：2000-02-15

申请号：US55433

申请日：1998-04-06

申请人： Chao-Cheng Chen ,  Chia-Shiung Tsai ,  Hun-Jan Tao

发明人： Chao-Cheng Chen ,  Chia-Shiung Tsai ,  Hun-Jan Tao

IPC分类号： H01L21/033 ,  H01L21/311 ,  H01L21/768 ,  H01L23/522 ,  H01L21/283

CPC分类号： H01L21/31144 ,  H01L21/76816 ,  H01L23/5226 ,  H01L21/0332 ,  H01L21/31116 ,  H01L2924/0002

摘要： A method is achieved for fabricating small contact holes in an interlevel dielectric (ILD) layer for integrated circuits. The method increases the ILD etch rate while reducing residue build-up on the contact hole sidewall. This provides a very desirable process for making contact holes small than 0.25 um in width. After depositing the ILD layer over the partially completed integrated circuit which includes patterned doped first polysilicon layers, a second polysilicon layer is deposited and doped with carbon by ion implantation. A photoresist mask is used to etch openings in the carbon doped polysilicon layer to form a hard mask. The photoresist is removed, and the contact holes are plasma etched in the ILD layer while free carbon released from the hard mask, during etching, reduces the free oxygen in the plasma. This results in an enhanced fluorine (F.sup.+) etch rate for the contact holes in the ILD layer and reduces the residue build-up on the sidewalls of the contact holes. The hard mask is anneal in O.sub.2 to form an oxide layer and any surface carbon is removed in a wet etch. Reliable metal plugs can now be formed by depositing a barrier layer, such as titanium (Ti) or titanium nitride (TiN) and a metal such as tungsten (W) and etching back or chemical/mechanical polishing back to the oxide layer.

摘要翻译： 实现了用于在用于集成电路的层间电介质（ILD）层中制造小接触孔的方法。 该方法增加了ILD蚀刻速率，同时减少了接触孔侧壁上的残留物积聚。 这提供了使接触孔宽度小于0.25μm的非常理想的方法。 在包括图案化掺杂的第一多晶硅层的部分完成的集成电路上沉积ILD层之后，通过离子注入沉积第二多晶硅层并掺杂碳。 光致抗蚀剂掩模用于蚀刻碳掺杂多晶硅层中的开口以形成硬掩模。 去除光致抗蚀剂，并且在ILD层中对接触孔进行等离子体蚀刻，而在蚀刻期间从硬掩模释放出的游离碳降低了等离子体中的游离氧。 这导致ILD层中的接触孔的氟（F +）蚀刻速率增加，并减少了接触孔的侧壁上的残留物积聚。 硬掩模在O 2中退火以形成氧化物层，并且在湿蚀刻中除去任何表面碳。 现在可以通过沉积诸如钛（Ti）或氮化钛（TiN）和诸如钨（W）的金属的阻挡层并且将氧化物层回蚀刻或化学/机械抛光来形成可靠的金属插塞。

公开(公告)号：US5981398A

公开(公告)日：1999-11-09

申请号：US58122

申请日：1998-04-10

申请人： Chia-Shiung Tsai ,  Chao-Cheng Chen ,  Hun-Jan Tao

发明人： Chia-Shiung Tsai ,  Chao-Cheng Chen ,  Hun-Jan Tao

IPC分类号： H01L21/3213 ,  H01L21/3065

CPC分类号： H01L21/32136 ,  H01L21/32137 ,  H01L21/32139

摘要： A method for forming a chlorine containing plasma etched patterned layer. There is first provided a substrate 10 employed within a microelectronics fabrication. There is then formed over the substrate a blanket target layer 12 formed of a material susceptible to etching within a second plasma employing a chlorine containing etchant gas composition. There is then formed upon the blanket target a blanket hard mask layer 14 formed of a material selected from the group consisting of silsesquioxane spin-on-glass (SOG) materials and amorphous carbon materials. There is then formed upon the blanket hard mask layer a patterned photoresist layer 16. There is then etched while employing the patterned photoresist layer as a first etch mask layer and while employing a first plasma employing a fluorine containing etchant gas composition the blanket hard mask layer to form a patterned hard mask layer. Finally, there is then etched while employing at least the patterned hard mask layer as a second etch mask layer and while employing the second plasma employing the chlorine containing etchant gas composition the blanket target layer to form the patterned target layer.

摘要翻译： 一种形成含氯等离子体蚀刻图案层的方法。 首先提供了在微电子制造中使用的衬底10。 然后在衬底上形成由使用含氯蚀刻剂气体组合物在第二等离子体内易于蚀刻的材料形成的覆盖层目标层12。 然后在橡皮布目标上形成由选自倍半硅氧烷旋涂玻璃（SOG）材料和无定形碳材料的材料形成的橡皮布硬掩模层14。 然后在橡皮布硬掩模层上形成图案化的光致抗蚀剂层16.然后在使用图案化的光致抗蚀剂层作为第一蚀刻掩模层的同时进行蚀刻，并且在使用含氟蚀刻剂气体组合物的第一等离子体的同时， 以形成图案化的硬掩模层。 最后，在使用至少图案化的硬掩模层作为第二蚀刻掩模层的同时蚀刻，并且在使用含氯蚀刻剂气体组合物的第二等离子体时，覆盖目标层以形成图案化目标层。

公开(公告)号：US06326296B1

公开(公告)日：2001-12-04

申请号：US09108867

申请日：1998-07-01

申请人： Chia Shiung Tsai ,  Hun-Jan Tao

发明人： Chia Shiung Tsai ,  Hun-Jan Tao

IPC分类号： H01L214763

CPC分类号： H01L21/76808 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/3144 ,  H01L21/3145 ,  H01L21/3185 ,  H01L2221/1036

摘要： A new method of forming a dual damascene interconnect is disclosed for manufacturing semiconductor substrates. A contact/via hole is first formed in a first dielectric layer formed over a substructure of a substrate having devices formed therein and/or metal layers formed thereon. The contact/via hole is filled with a protective material prior to forming a second dielectric layer. Conductive line opening is formed in the second dielectric layer and over the contact/via hole having the protective material in it. The protective material protects the edge of the contact/via hole from damage due to the second etching of the conductive line opening. Thus, a dual damascene structure is disclosed wherein the integrity of the edge of the contact/via hole is preserved, avoiding any reliability problems in the semiconductor product.

摘要翻译： 公开了一种形成双镶嵌互连的新方法，用于制造半导体衬底。 接触/通孔首先形成在形成在其上形成有器件和/或其上形成金属层的衬底的子结构之上的第一电介质层中。 在形成第二电介质层之前，接触/通孔填充有保护材料。 导电线路开口形成在第二电介质层中并且在其中具有保护材料的接触/通孔之上。 保护材料保护接触/通孔的边缘免受由于导电线开口的第二次蚀刻的损害。 因此，公开了一种双镶嵌结构，其中保留了接触/通孔的边缘的完整性，避免了半导体产品中的任何可靠性问题。

公开(公告)号：US06472335B1

公开(公告)日：2002-10-29

申请号：US09175019

申请日：1998-10-19

申请人： Chia-Shiung Tsai ,  Yao-Yi Cheng ,  Hun-Jan Tao

发明人： Chia-Shiung Tsai ,  Yao-Yi Cheng ,  Hun-Jan Tao

IPC分类号： H01L2131

CPC分类号： H01L21/0214 ,  H01L21/02118 ,  H01L21/022 ,  H01L21/02343 ,  H01L21/31111 ,  H01L21/312 ,  H01L21/3122 ,  H01L21/3124 ,  H01L21/3144 ,  H01L21/31629 ,  H01L21/3185 ,  H01L21/76801 ,  Y10S438/906 ,  Y10S438/958 ,  Y10S438/964

摘要： The present invention provides a method improving the adhesion between inter metal dielectric (IMD) layers by performing a HF dip etch to treat the surface of an oxide, silicon nitride or Silicon oxynitride insulating layer before an overlying low-K layer is formed. The present invention provides a method of fabricating a low-K IMD layer 20 over an oxide, Silicon oxynitride (SiON), or nitride IMD layer 14 with improved adhesion. First, a 1st inter metal dielectric (IMD) layer 14 is formed over a substrate. Next, the invention's novel HF dip etch is performed on the 1st IMD layer 14 to form a treated surface 16. Next, a 2nd BMD layer composed of a low-K material is formed over the rough surface 16 of the 1st IMD layer 14. The treated surface 16 improves the adhesion between a 1st IMD layer oxide (oxide, SiN or SiON) and a low k layer. Subsequent photoresist strip steps do not cause the 1st IMI layer 14 and the 2nd IMD layer 20 (low-K dielectric) to peel.

摘要翻译： 本发明提供一种通过在形成上覆低K层之前进行HF浸渍蚀刻来处理氧化物，氮化硅或氮氧化硅绝缘层的表面来改善金属间电介质（IMD）层之间的粘合力的方法。 本发明提供了一种在氧化物，氮氧化硅（SiON）或氮化物IMD层14上制备低K IMD层20的方法，其具有改善的粘合性。 首先，在衬底上形成第一金属间介电层（IMD）层14。 接下来，在第一IMD层14上进行本发明的新型HF浸渍蚀刻以形成处理表面16.接下来，在第一IMD层14的粗糙表面16上形成由低K材料构成的第二BMD层。 经处理的表面16改善了第一IMD层氧化物（氧化物，SiN或SiON）和低k层之间的粘合性。 随后的光刻胶条步骤不会导致第一IMI层14和第二IMD层20（低K电介质）剥离。

公开(公告)号：US6165881A

公开(公告)日：2000-12-26

申请号：US177185

申请日：1998-10-23

申请人： Hun-Jan Tao ,  Chia-Shiung Tsai

发明人： Hun-Jan Tao ,  Chia-Shiung Tsai

IPC分类号： H01L21/027 ,  H01L21/311 ,  H01L21/336 ,  H01L21/4763

CPC分类号： H01L29/665 ,  H01L21/0276 ,  H01L21/31116

摘要： I A method is achieved for removing a hardmask from a feature on a semiconductor wafer. The method comprises the following phases: depositing a buffer layer overall; etching back the buffer layer in an etching apparatus to expose the hardmask; etching the hardmask in the etching apparatus; and etching of the remaining buffer layer in the etching apparatus.

摘要翻译： I实现了从半导体晶片上的特征去除硬掩模的方法。 该方法包括以下阶段：整体沉积缓冲层; 在蚀刻装置中蚀刻缓冲层以暴露硬掩模; 在蚀刻装置中蚀刻硬掩模; 并蚀刻在蚀刻装置中的剩余缓冲层。

公开(公告)号：US6129091A

公开(公告)日：2000-10-10

申请号：US725804

申请日：1996-10-04

申请人： Kuei-Ying Lee ,  Hun-Jan Tao ,  Chia-Shiung Tsai

发明人： Kuei-Ying Lee ,  Hun-Jan Tao ,  Chia-Shiung Tsai

IPC分类号： H01L21/00 ,  B08B3/08 ,  B08B3/12

CPC分类号： H01L21/67028

摘要： Current aqueous methods for removal of polymeric materials from the sidewalls of trenches etched into silicon wafers by reactive-ion-etching are inadequate for treating deep trenches having high aspect ratios. Spin-dry operations performed after the aqueous etching are incapable of completely removing rinse water and ionic species from these deep trenches, thereby leaving pockets of liquid. Subsequent evaporation of these pockets results in the concentration and eventual precipitation of residual ionic species creating watermarks. A two stage cleaning method is described in which the first stage dissolves the sidewall polymer and the second stage draws ionic species strongly chemisorbed onto the silicon surfaces into solution. A key feature of the method is that the wafer surface is not permitted to dry until after the final rinse.

摘要翻译： 目前的用于通过反应离子蚀刻从蚀刻到硅晶片的沟槽的侧壁上去除聚合材料的水性方法不足以处理具有高纵横比的深沟槽。 在水蚀刻之后执行的旋转干燥操作不能从这些深沟槽中完全去除漂洗水和离子物质，从而留下一些液体。 随后蒸发这些口袋导致产生水印的残留离子物质的浓度和最终沉淀。 描述了两阶段清洗方法，其中第一阶段溶解侧壁聚合物，第二阶段将离子物质强吸附在硅表面上成溶液。 该方法的一个关键特征是晶片表面不允许干燥直到最后冲洗。