公开(公告)号：US20050258864A1

公开(公告)日：2005-11-24

申请号：US10852390

申请日：2004-05-24

申请人： Ker-Mih Chen ,  Kuo-Ji Chen

发明人： Ker-Mih Chen ,  Kuo-Ji Chen

IPC分类号： H03K3/356 ,  H03K17/10 ,  H03K19/094

CPC分类号： H03K3/356113 ,  H03K17/102

摘要： An integrated circuit for level-shifting voltage signals comprises an input/output pad, and an input/output circuit coupled to the output pad having a plurality of devices operating with a bias supply voltage operable to shift between the range of the bias supply voltage to the range of an input/output supply voltage that is higher than the bias supply voltage.

摘要翻译： 用于电平移动电压信号的集成电路包括输入/​​输出焊盘和耦合到输出焊盘的输入/输出电路，该输出/输出电路具有多个器件，工作在偏置电源电压下工作，偏置电源电压可操作以在偏置电源电压的范围 输入/输出电源电压的范围高于偏置电源电压。

公开(公告)号：US09425616B2

公开(公告)日：2016-08-23

申请号：US13184290

申请日：2011-07-15

申请人： Yen-Lin Liu ,  Kuo-Ji Chen ,  Tzu-Yi Yang

发明人： Yen-Lin Liu ,  Kuo-Ji Chen ,  Tzu-Yi Yang

IPC分类号： H02H9/00 ,  H02H9/04 ,  H02H3/22

CPC分类号： H02H9/046

摘要： An RC triggered ESD protection device comprises a discharge transistor, a driver circuit and a trigger circuit. The trigger circuit comprises a plurality of native NMOS transistors connected in parallel with a plurality of PMOS transistors operating as resistors. The relatively small resistance of the plurality of native NMOS transistors helps to keep a stable RC time constant value so that the ESD protection device can avoid a leakage current during a power up operation.

摘要翻译： RC触发ESD保护装置包括放电晶体管，驱动电路和触发电路。 触发电路包括与作为电阻器操作的多个PMOS晶体管并联连接的多个天然NMOS晶体管。 多个天然NMOS晶体管的相对小的电阻有助于保持稳定的RC时间常数值，使得ESD保护装置可以在上电操作期间避免漏电流。

公开(公告)号：US08587074B2

公开(公告)日：2013-11-19

申请号：US13101727

申请日：2011-05-05

申请人： Harry-Hak-Lay Chuang ,  Ming-Hsiang Song ,  Kuo-Ji Chen ,  Ming Zhu ,  Po-Nien Chen ,  Bao-Ru Young

发明人： Harry-Hak-Lay Chuang ,  Ming-Hsiang Song ,  Kuo-Ji Chen ,  Ming Zhu ,  Po-Nien Chen ,  Bao-Ru Young

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L27/0266 ,  H01L29/0653 ,  H01L29/402 ,  H01L29/41775 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/4966 ,  H01L29/4983 ,  H01L29/66484 ,  H01L29/66545 ,  H01L29/66659 ,  H01L29/66666 ,  H01L29/66681 ,  H01L29/7835

摘要： A device includes a drain, a source, and a gate stack. The gate stack has a gate dielectric layer, a gate conductive layer immediately on top of the gate dielectric layer, and first gate and a second gate layer that are immediately on top of the gate conductive layer. The first gate layer has a first resistance higher than a second resistance of the second gate layer. The second gate layer is conductive, is electrically coupled with the gate conductive layer, and has a contact terminal configured to serve as a gate contact terminal for the device. Fabrication methods of the gate stack are also disclosed.

摘要翻译： 一种器件包括漏极，源极和栅极叠层。 栅极堆叠具有栅极电介质层，立即在栅极电介质层的顶部上的栅极导电层，以及立即在栅极导电层顶部上的第一栅极和第二栅极层。 第一栅极层具有比第二栅极层的第二电阻高的第一电阻。 第二栅极层是导电的，与栅极导电层电耦合，并且具有被配置为用作器件的栅极接触端子的接触端子。 还公开了栅极堆叠的制造方法。

公开(公告)号：US20130182356A1

公开(公告)日：2013-07-18

申请号：US13349962

申请日：2012-01-13

申请人： Tzu-Yi Yang ,  Kuo-Ji Chen

发明人： Tzu-Yi Yang ,  Kuo-Ji Chen

IPC分类号： H02H9/04

CPC分类号： H02H9/046

摘要： Some embodiments relate to an area efficient electrostatic discharge (ESD) clamp comprising an RC trigger circuit, having one or more low-voltage, thin-oxide devices, which is configured to operate with a high-voltage power supply. In some embodiments, the ESD clamp comprises an RC trigger circuit connected between a first circuit node having a first voltage and a second circuit node having a second voltage. The RC trigger circuit comprises a resistive element connected in series with a thin-oxide MOS capacitor. The MOS capacitor has a source and drain connected to an intermediate supply voltage between the first and second voltage, and a body connected to the second voltage. By connecting the source and drain to the intermediate supply voltage, the thin-oxide MOS capacitor is able to reliably operate with a high-voltage power supply.

摘要翻译： 一些实施例涉及包括具有一个或多个低压，薄氧化物装置的RC触发电路的区域有效的静电放电（ESD）钳位，其被配置为利用高压电源进行操作。 在一些实施例中，ESD钳位包括连接在具有第一电压的第一电路节点和具有第二电压的第二电路节点之间的RC触发电路。 RC触发电路包括与薄氧化物MOS电容器串联连接的电阻元件。 MOS电容器具有连接到第一和第二电压之间的中间电源电压的源极和漏极以及连接到第二电压的主体。 通过将源极和漏极连接到中间电源电压，薄氧化物MOS电容器能够使用高压电源可靠地工作。

公开(公告)号：US20100033884A1

公开(公告)日：2010-02-11

申请号：US12186400

申请日：2008-08-05

申请人： Tso-Hung Fan ,  Kuo-Ji Chen

发明人： Tso-Hung Fan ,  Kuo-Ji Chen

IPC分类号： H02H9/04

CPC分类号： H02H9/046

摘要： This invention discloses a trigger circuit for an electrostatic discharge (ESD) protection device, the ESD protection device being turned on during an ESD event and being turned off during a normal operation, the trigger circuit comprises a voltage sensing circuit coupled to a bonding pad, the voltage sensing circuit being configured to produce a first predetermined voltage during a ESD event, and to produce a second predetermined voltage complimentary to the first predetermined voltage during a normal operation, and a voltage converting circuit having a positive feedback circuit and coupled between the voltage sensing circuit and the ESD protection device for converting the first predetermined voltage to a third predetermined voltage for turning on the ESD protection device, and for converting the second predetermined voltage to a fourth predetermined voltage for turning off the ESD protection device.

摘要翻译： 本发明公开了一种用于静电放电（ESD）保护装置的触发电路，ESD保护装置在ESD事件期间被接通并且在正常操作期间被断开，触发电路包括耦合到接合焊盘的电压感测电路， 电压感测电路被配置为在ESD事件期间产生第一预定电压，并且在正常操作期间产生与第一预定电压互补的第二预定电压，以及电压转换电路，具有正反馈电路并耦合在电压 感测电路和用于将第一预定电压转换为用于接通ESD保护装置的第三预定电压的ESD保护装置，以及用于将第二预定电压转换为用于关闭ESD保护装置的第四预定电压。

公开(公告)号：US20100026366A1

公开(公告)日：2010-02-04

申请号：US12494082

申请日：2009-06-29

申请人： Guang-Cheng Wang ,  Ker-Min Chen ,  Kuo-Ji Chen

发明人： Guang-Cheng Wang ,  Ker-Min Chen ,  Kuo-Ji Chen

IPC分类号： H03L5/00

CPC分类号： H03K3/35613 ,  H03K3/012

摘要： A voltage level shifting circuit for an integrated circuit system having an internal low voltage power supply (VCCL) and an external high voltage power supply (VCCH) is disclosed, the voltage level shifting circuit comprises a pair of cross coupled PMOS transistors connected to the VCCH, a NMOS transistor with a source connected to a ground (VSS) and a gate connected to a first signal swinging between the VCCL and the VSS, and a switching device coupled between a drain of one of the pair of PMOS transistors and a drain of the NMOS transistor, wherein the pair of PMOS transistors are high voltage transistors and the switching device is off when the VCCL is below a predetermined voltage level, and the switching device is on when the VCCL is above the predetermined voltage level.

摘要翻译： 公开了一种具有内部低压电源（VCCL）和外部高压电源（VCCH）的集成电路系统的电压电平移动电路，电压电平移位电路包括一对连接到VCCH的交叉耦合PMOS晶体管 ，源极连接到地（VSS）的NMOS晶体管和连接到在VCCL和VSS之间摆动的第一信号的栅极，以及耦合在一对PMOS晶体管之一的漏极和 NMOS晶体管，其中一对PMOS晶体管是高压晶体管，并且当VCCL低于预定电压电平时，开关器件关断，并且当VCCL高于预定电压电平时，开关器件导通。

公开(公告)号：US07271627B2

公开(公告)日：2007-09-18

申请号：US11236153

申请日：2005-09-26

申请人： Kuo-Ji Chen

发明人： Kuo-Ji Chen

IPC分类号： H03K3/00

CPC分类号： H03K19/018521 ,  H03K19/0027 ,  H03K19/00384

摘要： An input buffer includes a signal passing module for generating a first output signal in response to the input signal based on a comparison between the input signal and a first supply voltage thereof; a regulating module having a first input terminal receiving the input signal and a second input terminal receiving the first output signal for generating a second output signal within a first predetermined voltage range; and a level down module for generating a third output signal within a second predetermined voltage range for the core circuitry in response to the second output signal. The input signal passes through the signal passing module with a substantial voltage drop when a voltage level of the input signal is substantially greater than the first supply voltage, and without a substantial voltage drop when the voltage level of the same is less than or equal to the first supply voltage.

公开(公告)号：US20050270079A1

公开(公告)日：2005-12-08

申请号：US10859726

申请日：2004-06-03

申请人： Kuo-Ji Chen ,  Tsung-Hsing Yu ,  Ker-Min Chen

发明人： Kuo-Ji Chen ,  Tsung-Hsing Yu ,  Ker-Min Chen

IPC分类号： H03K5/153 ,  H03K19/00 ,  H03K19/0185 ,  H03L5/00

CPC分类号： H03K19/018521 ,  H03K19/0027

摘要： An input buffer for interfacing a high voltage signal received at an input node to a low voltage circuit comprising low voltage devices is provided. The buffer includes a threshold adjustment circuit including an inverter coupled to a threshold adjusted output node. The inverter includes low voltage devices and is coupled between a high supply voltage node and a ground node. The inverter includes a first and second transistors having biasing nodes coupled to a low voltage supply node of the low voltage circuit and coupled to the threshold adjusted output node. The adjustment circuit provides at the threshold adjusted output node an inverted signal corresponding to the high voltage input signal. The buffer also includes a level shifting circuit including low voltage devices and provides a low voltage signal corresponding to the high voltage input signal in response to said inverted signal.

摘要翻译： 提供了一种用于将在输入节点处接收的高电压信号与包括低电压装置的低压电路接口的输入缓冲器。 缓冲器包括阈值调整电路，其包括耦合到阈值调整输出节点的反相器。 逆变器包括低电压器件，并且耦合在高电源节点和接地节点之间。 反相器包括第一和第二晶体管，其具有耦合到低压电路的低电压电源节点并耦合到阈值调整输出节点的偏置节点。 调整电路在阈值调整后的输出节点提供与高电压输入信号相对应的反相信号。 缓冲器还包括电平移动电路，其包括低电压装置，并且响应于所述反相信号提供对应于高电压输入信号的低电压信号。

公开(公告)号：US09385241B2

公开(公告)日：2016-07-05

申请号：US12766186

申请日：2010-04-23

申请人： Shu-Chuan Lee ,  Kuo-Ji Chen ,  Wade Ma

发明人： Shu-Chuan Lee ,  Kuo-Ji Chen ,  Wade Ma

IPC分类号： H01L23/62 ,  H01L29/861 ,  H01L27/02 ,  H01L29/16 ,  H01L29/20

CPC分类号： H01L27/0262 ,  H01L27/0277 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/861

摘要： An electrostatic discharge (ESD) protection circuit coupled with an input/output (I/O) pad is provided. The ESD protection circuit includes a first field oxide device coupled between a first terminal that is capable of providing a first supply voltage and the I/O pad. The first field oxide device includes a drain end having a first type of dopant and a source end having the first type of dopant. The first field oxide device includes a first doped region having a second type of dopant disposed adjacent to the drain end of the first field oxide device and a second doped region having the second type of dopant disposed adjacent to the source end of the first field oxide device.

摘要翻译： 提供与输入/输出（I / O）焊盘耦合的静电放电（ESD）保护电路。 ESD保护电路包括耦合在能够提供第一电源电压的第一端子和I / O焊盘之间的第一场氧化物装置。 第一场氧化物器件包括具有第一类掺杂剂的漏极端和具有第一类掺杂剂的源极端。 第一场氧化物器件包括具有邻近第一场氧化物器件的漏极端设置的第二类型掺杂物的第一掺杂区域和具有邻近第一场氧化物源极端的第二类型掺杂物的第二掺杂区域 设备。

公开(公告)号：US09184586B2

公开(公告)日：2015-11-10

申请号：US13533059

申请日：2012-06-26

申请人： Wen-Han Wang ,  Kuo-Ji Chen

发明人： Wen-Han Wang ,  Kuo-Ji Chen

IPC分类号： H02H9/04

CPC分类号： H02H9/046 ,  Y10T29/49117

摘要： Some embodiments of the present disclosure relate to a low-power, area efficient ESD protection device that provides ESD protection to an ESD susceptible circuit. The ESD protection device has a trigger circuit with a resistor. The resistor has a first terminal connected to the first external pin and a second terminal connected directly to a gate of a SiGe based PMOS shunt transistor. The trigger circuit generates a trigger signal that drives the gate of the PMOS device to shunt power away from the ESD susceptible circuit when an ESD event is present. The SiGe based PMOS shunt transistor has a lower gate leakage than a conventional NMOS shunt transistors, thereby providing for an ESD circuit with a low leakage current at small gate lengths.

摘要翻译： 本公开的一些实施例涉及向ESD敏感电路提供ESD保护的低功率，区域有效的ESD保护装置。 ESD保护器件具有带电阻器的触发电路。 电阻器具有连接到第一外部引脚的第一端子和直接连接到基于SiGe的PMOS分流晶体管的栅极的第二端子。 当存在ESD事件时，触发电路产生驱动PMOS器件的栅极的触发信号，以将电源从ESD易受损害的电路分流。 基于SiGe的PMOS分流晶体管具有比常规NMOS分流晶体管更低的栅极泄漏，从而在小栅极长度处提供具有低漏电流的ESD电路。