公开(公告)号：US20070082503A1

公开(公告)日：2007-04-12

申请号：US11163218

申请日：2005-10-11

Applicant: Yun-Ren Wang ,  Ying-Wei Yen ,  Chien-Hua Lung ,  Shu-Yen Chan ,  Kuo-Tai Huang

Inventor： Yun-Ren Wang ,  Ying-Wei Yen ,  Chien-Hua Lung ,  Shu-Yen Chan ,  Kuo-Tai Huang

IPC: H01L21/31 ,  H01L21/469

CPC classification number: H01L21/02332 ,  H01L21/02337 ,  H01L21/0234 ,  H01L21/3144

Abstract: A method of fabricating a dielectric layer is described. A substrate is provided, and a dielectric layer is formed over the substrate. The dielectric layer is performed with a nitridation process. The dielectric layer is performed with a first annealing process. A first gas used in the first annealing process includes inert gas and oxygen. The first gas has a first partial pressure ratio of inert gas to oxygen. The dielectric layer is performed with the second annealing process. A second gas used in the second annealing includes inert gas and oxygen. The second gas has a second partial pressure ratio of inert gas to oxygen, and the second partial pressure ratio is smaller than the first partial pressure ratio. At least one annealing temperature of the two annealing processes is equal to or greater than 950° C. The invention improves uniformity of nitrogen dopants distributed in dielectric layer.

Abstract translation: 描述制造介电层的方法。 提供衬底，并且在衬底上形成电介质层。 介电层通过氮化处理进行。 介电层通过第一退火工艺进行。 在第一退火工艺中使用的第一种气体包括惰性气体和氧气。 第一气体具有惰性气体与氧的第一分压比。 介电层通过第二退火工艺进行。 在第二退火中使用的第二气体包括惰性气体和氧气。 第二气体具有惰性气体与氧气的第二分压比，第二分压比小于第一分压比。 两个退火工艺的至少一个退火温度等于或大于950℃。本发明改善了分布在介电层中的氮掺杂剂的均匀性。

公开(公告)号：US06555425B2

公开(公告)日：2003-04-29

申请号：US09880519

申请日：2001-06-12

Applicant: Kuo-Tai Huang ,  Ellen Cheng

Inventor： Kuo-Tai Huang ,  Ellen Cheng

IPC: H01L218238

CPC classification number: H01L29/66583 ,  H01L21/28114 ,  H01L29/41783 ,  H01L29/42376 ,  H01L29/6656 ,  H01L29/7834

Abstract: A method of manufacturing a transistor. The method comprising the steps of providing a substrate. The substrate comprises a gate oxide layer formed thereon, a polysilicon layer formed on the gate oxide layer, an offset spacer formed on a sidewall of the polysilicon layer and the gate oxide layer and a source/drain formed in the substrate. A conformal dielectric layer is formed over the polysilicon layer, the offset spacer and the source/drain. A spacer is formed on the sidewall of a portion of the conformal dielectric layer over the offset spacer. A portion of the conformal dielectric layer is removed to expose the polysilicon layer and the source/drain. A selective epitaxial growth process is performed to form an epitaxial layer on the polysilicon layer and the source/drain. A portion of the epitaxial layer on the polysilicon layer, the polysilicon layer and the gate oxide layer together form a T-type gate structure.

公开(公告)号：US06291295B1

公开(公告)日：2001-09-18

申请号：US09316979

申请日：1999-05-24

Applicant: Kuo-Tai Huang ,  Tri-Rung Yew ,  Water Lur

Inventor： Kuo-Tai Huang ,  Tri-Rung Yew ,  Water Lur

IPC: H01L218242

CPC classification number: H01L28/60 ,  H01L21/02129 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/02332 ,  H01L21/3105 ,  H01L21/31625 ,  H01L21/76895 ,  H01L27/10852 ,  H01L28/84

Abstract: A method of fabricating a capacitor. An isolation layer is formed on a substrate. An ion implantation step is performed. The isolation layer is patterned to form an opening in the isolation layer. The opening exposes a portion of the substrate. A patterned conductive layer is formed on the isolation layer to fill the opening. A hemispherical grained silicon layer is performed on the conductive layer. In addition, the step order of the ion implantation step can be changed. The ion implantation can also be performed after the opening is formed.

Abstract translation: 一种制造电容器的方法。 在基板上形成隔离层。 执行离子注入步骤。 隔离层被图案化以在隔离层中形成开口。 开口露出基底的一部分。 在隔离层上形成图案化的导电层以填充开口。 在导电层上进行半球状的硅层。 此外，可以改变离子注入步骤的步骤顺序。 离子注入也可以在开口形成之后进行。

公开(公告)号：US06235606B1

公开(公告)日：2001-05-22

申请号：US09225031

申请日：1999-01-04

Applicant: Michael W C Huang ,  Kuo-Tai Huang ,  Hsiao-Ling Lu ,  Tri-Rung Yew

Inventor： Michael W C Huang ,  Kuo-Tai Huang ,  Hsiao-Ling Lu ,  Tri-Rung Yew

IPC: H01L2176

CPC classification number: H01L21/76897 ,  H01L21/76224

Abstract: A method for fabricating a shallow trench isolation. A pad oxide layer and a mask layer are formed over a substrate. The pad oxide layer, the mask layer, and the substrate are patterned to form a trench exposing a portion of the substrate. A liner oxide layer is formed on the substrate exposed by the trench. An isolation layer is formed over the substrate to cover the liner oxide layer. The isolation layer is conformal to the trench. An oxide layer is formed over the substrate to fill the trench. A portion of the oxide layer and the isolation layer is removed until the mask layer is exposed. The mask layer and the pad oxide layer are removed to form a shallow trench isolation.

Abstract translation: 一种制造浅沟槽隔离的方法。 在衬底上形成衬垫氧化物层和掩模层。 将衬垫氧化物层，掩模层和衬底图案化以形成暴露衬底的一部分的沟槽。 在由沟槽暴露的衬底上形成衬里氧化物层。 在衬底上形成隔离层以覆盖衬里氧化物层。 隔离层与沟槽保形。 在衬底上形成氧化物层以填充沟槽。 除去氧化物层和隔离层的一部分直到掩模层露出。 去除掩模层和焊盘氧化物层以形成浅沟槽隔离。

公开(公告)号：US06078492A

公开(公告)日：2000-06-20

申请号：US128364

申请日：1998-08-03

Applicant: Kuo-Tai Huang ,  Wen-Yi Hsieh ,  Tri-Rung Yew

Inventor： Kuo-Tai Huang ,  Wen-Yi Hsieh ,  Tri-Rung Yew

IPC: H01L27/108 ,  H01L21/02 ,  H01L21/8242 ,  H01G4/30 ,  H01G4/008

CPC classification number: H01L27/10852 ,  H01L28/82

Abstract: A structure of a capacitor includes two gates and a commonly used source/drain region on a substrate. Then, a pitted self align contact window (PSACW) partly exposes the commonly used source/drain region. Then an glue/barrier layer and a lower electrode of the capacitor are over the PSACW. Then a dielectric thin film with a material having high dielectric constant is over the lower electrode. Then, an upper electrode is over the dielectric thin film to complete a capacitor, which has a structure of metal insulator metal with a shape like the PSACW.

Abstract translation: 电容器的结构包括两个栅极和在衬底上的常用源极/漏极区域。 然后，凹陷的自对准接触窗口（PSACW）部分地暴露常用的源极/漏极区域。 然后电容器的胶/阻挡层和下电极在PSACW之上。 然后，具有高介电常数的材料的电介质薄膜在下电极之上。 然后，上电极在电介质薄膜的上方，以完成电容器，该电容器具有类似于PSACW形状的金属绝缘体金属的结构。

公开(公告)号：US5956598A

公开(公告)日：1999-09-21

申请号：US164736

申请日：1998-10-01

Applicant: Kuo-Tai Huang ,  Gwo-Shii Yang ,  Tri-Rung Yew ,  Water Lur

Inventor： Kuo-Tai Huang ,  Gwo-Shii Yang ,  Tri-Rung Yew ,  Water Lur

IPC: H01L21/762 ,  H01L21/76

CPC classification number: H01L21/76224

Abstract: A semiconductor fabrication method is provided for fabricating a shallow-trench isolation (STI) structure with a rounded corner in integrated circuits through a rapid thermal process (RTP). In the fabrication of the STI structure, a sharp corner is often undesirably formed. This sharp corner , if not eliminated, causes the occurrence of a leakage current when the resultant IC device is in operation that significantly degrades the performance of the resultant IC device. To eliminate this sharp corner , an RTP is performed at a temperature of above 1,100.degree. C., which temperature is higher than the glass transition temperature of the substrate, for about 1 to 2 minutes. The result is that the surface of the substrate is oxidized into an sacrificial oxide layer and the sharp corner is deformed into a rounded shape with a larger convex radius of curvature. This allows the problems arising from the existence of the sharp corner to be substantially eliminated. Compared to the prior art, this method not only is more simplified in process, but also allows a considerable saving in thermal budget, which makes this method more cost-effective to implement than the prior art.

Abstract translation: 提供半导体制造方法，用于通过快速热处理（RTP）在集成电路中制造具有圆角的浅沟槽隔离（STI）结构。 在STI结构的制造中，通常不希望地形成尖锐的拐角。 如果不消除这个尖角，则当所得到的IC器件运行时会导致泄漏电流的发生，这显着降低了所得IC器件的性能。 为了消除这个尖角，RTP在高于1100℃的温度下进行，该温度高于基板的玻璃化转变温度约1至2分钟。 其结果是，衬底的表面被氧化成牺牲氧化物层，并且尖角变形为具有较大凸曲率半径的圆形形状。 这允许基本上消除由尖角存在引起的问题。 与现有技术相比，该方法不仅在过程中更简化，而且还可以大大节省热预算，这使得该方法比现有技术更具成本效益。

公开(公告)号：US08736016B2

公开(公告)日：2014-05-27

申请号：US11759791

申请日：2007-06-07

Applicant: Mong-Song Liang ,  Tze-Liang Lee ,  Kuo-Tai Huang ,  Chao-Cheng Chen ,  Hao-Ming Lien ,  Chih-Tang Peng

Inventor： Mong-Song Liang ,  Tze-Liang Lee ,  Kuo-Tai Huang ,  Chao-Cheng Chen ,  Hao-Ming Lien ,  Chih-Tang Peng

IPC: H01L29/78

CPC classification number: H01L29/1054 ,  H01L21/76224 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7846

Abstract: An isolation trench having localized stressors is provided. In accordance with embodiments of the present invention, a trench is formed in a substrate and partially filled with a dielectric material. In an embodiment, the trench is filled with a dielectric layer and a planarization step is performed to planarize the surface with the surface of the substrate. The dielectric material is then recessed below the surface of the substrate. In the recessed portion of the trench, the dielectric material may remain along the sidewalls or the dielectric material may be removed along the sidewalls. A stress film, either tensile or compressive, may then be formed over the dielectric material within the recessed portion. The stress film may also extend over a transistor or other semiconductor structure.

Abstract translation: 提供了具有局部应力源的隔离沟槽。 根据本发明的实施例，在衬底中形成沟槽并且部分地填充有电介质材料。 在一个实施例中，沟槽被填充有电介质层，并且执行平面化步骤以使其与衬底的表面平坦化。 然后将电介质材料凹入到衬底的表面下方。 在沟槽的凹陷部分中，电介质材料可以沿着侧壁保留，或者电介质材料可以沿侧壁去除。 然后可以在凹陷部分内的电介质材料上形成拉伸或压缩的应力膜。 应力膜也可以在晶体管或其它半导体结构上延伸。

公开(公告)号：US08324090B2

公开(公告)日：2012-12-04

申请号：US12338787

申请日：2008-12-18

Applicant: Yuri Masuoka ,  Peng-Fu Hsu ,  Huan-Tsung Huang ,  Kuo-Tai Huang ,  Yong-Tian Hou ,  Carlos H. Diaz

Inventor： Yuri Masuoka ,  Peng-Fu Hsu ,  Huan-Tsung Huang ,  Kuo-Tai Huang ,  Yong-Tian Hou ,  Carlos H. Diaz

IPC: H01L21/4763 ,  H01L25/11 ,  H01L29/78

CPC classification number: H01L29/4925 ,  H01L21/28061 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/823842 ,  H01L29/513 ,  H01L29/517

Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor substrate having a first active region and a second active region, providing a semiconductor substrate having a first region and a second region, forming a high-k dielectric layer over the semiconductor substrate, forming a first capping layer and a second capping layer over the high-k dielectric layer, the first capping layer overlying the first region and the second capping layer overlying the second region, forming a layer containing silicon (Si) over the first and second capping layers, forming a metal layer over the layer containing Si, and forming a first gate stack over the first region and a second gate stack over the second active region. The first gate stack includes the high-k dielectric layer, the first capping layer, the layer containing Si, and the metal layer and the second gate stack includes the high-k dielectric layer, the second capping layer, the layer containing Si, and the metal layer.

Abstract translation: 本公开提供了制造半导体器件的方法。 该方法包括提供具有第一有源区和第二有源区的半导体衬底，提供具有第一区域和第二区域的半导体衬底，在半导体衬底上形成高k电介质层，形成第一覆盖层和 第二覆盖层覆盖在高k电介质层上，覆盖第一区域的第一覆盖层和覆盖第二区域的第二封盖层，在第一和第二覆盖层上形成含有硅（Si）的层，形成金属层 所述层包含Si，并且在所述第一区域上形成第一栅极堆叠，并且在所述第二有源区域上形成第二栅极堆叠。 第一栅极堆叠包括高k电介质层，第一覆盖层，含有Si的层，金属层和第二栅极堆叠包括高k电介质层，第二覆盖层，含有Si的层和 金属层。

公开(公告)号：US20120164822A1

公开(公告)日：2012-06-28

申请号：US13408016

申请日：2012-02-29

Applicant: Yih-Ann Lin ,  Ryan Chia-Jen Chen ,  Chien-Hao Chen ,  Kuo-Tai Huang ,  Yi-Hsing Chen ,  Jr Jung Lin

Inventor： Yih-Ann Lin ,  Ryan Chia-Jen Chen ,  Chien-Hao Chen ,  Kuo-Tai Huang ,  Yi-Hsing Chen ,  Jr Jung Lin

IPC: H01L21/28

CPC classification number: H01L21/823828 ,  H01L21/3221 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517

Abstract: Methods of fabricating semiconductor devices with high-k/metal gate features are disclosed. In some instances, methods of fabricating semiconductor devices with high-k/metal gate features are disclosed that prevent or reduce high-k/metal gate contamination of non-high-k/metal gate wafers and production tools. In some embodiments, the method comprises forming an interfacial layer over a semiconductor substrate on a front side of the substrate; forming a high-k dielectric layer and a capping layer over the interfacial layer; forming a metal layer over the high-k and capping layers; forming a polysilicon layer over the metal layer; and forming a dielectric layer over the semiconductor substrate on a back side of the substrate.

Abstract translation: 公开了制造具有高k /金属栅极特征的半导体器件的方法。 在一些情况下，公开了制造具有高k /金属栅极特征的半导体器件的方法，其防止或减少非高k /金属栅极晶片和生产工具的高k /金属栅极污染。 在一些实施例中，该方法包括在衬底的前侧上的半导体衬底上形成界面层; 在界面层上形成高k电介质层和覆盖层; 在高k和覆盖层上形成金属层; 在所述金属层上形成多晶硅层; 以及在所述衬底的背面上在所述半导体衬底上形成介电层。

公开(公告)号：US20100044800A1

公开(公告)日：2010-02-25

申请号：US12589421

申请日：2009-10-23

Applicant: Joshua Tseng ,  Kang-Cheng Lin ,  Ji-Yi Yang ,  Kuo-Tai Huang ,  Ryan Chia-Jen Chen

Inventor： Joshua Tseng ,  Kang-Cheng Lin ,  Ji-Yi Yang ,  Kuo-Tai Huang ,  Ryan Chia-Jen Chen

IPC: H01L27/092

CPC classification number: H01L21/823857 ,  H01L21/823842

Abstract: A metal gate/high-k dielectric semiconductor device provides an NMOS gate structure and a PMOS gate structure formed on a semiconductor substrate. The NMOS gate structure includes a high-k gate dielectric treated with a dopant impurity such as La and the high-k gate dielectric material of the PMOS gate structure is deficient of this dopant impurity and further includes a work function tuning layer over the high-k gate dielectric.

Abstract translation: 金属栅极/高k电介质半导体器件提供形成在半导体衬底上的NMOS栅极结构和PMOS栅极结构。 NMOS栅极结构包括用诸如La的掺杂剂杂质处理的高k栅极电介质，并且PMOS栅极结构的高k栅极电介质材料缺乏该掺杂杂质，并且还包括高功率调制层， k栅极电介质。