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44 条记录 (耗时 0.034 秒)

    Method of forming self-aligned silicide in semiconductor device
    21.
    发明授权
    Method of forming self-aligned silicide in semiconductor device 有权
    在半导体器件中形成自对准硅化物的方法

    公开(公告)号：US06329276B1

    公开(公告)日：2001-12-11

    申请号：US09392470

    申请日：1999-09-09

    申请人： Ja-Hum Ku ,  Soo-Geun Lee ,  Chul-Sung Kim ,  Tae-Wook Seo ,  Eung-Joon Lee ,  Joo-Hyuk Chung

    发明人： Ja-Hum Ku ,  Soo-Geun Lee ,  Chul-Sung Kim ,  Tae-Wook Seo ,  Eung-Joon Lee ,  Joo-Hyuk Chung

    IPC分类号： H01L213205

    CPC分类号： H01L29/665 ,  H01L21/28518

    摘要： There is provided a semiconductor device fabrication method. In the method, a gate layer is formed on a semiconductor substrate and patterned to form a first resultant structure, a metal layer is formed on the first resultant structure, a capping layer is formed on the metal layer, a metal silicide is formed on the gate layer by heating the substrate at a first temperature, unreacted metal layer and first capping layer are removed to form a second resultant structure, a second capping layer is formed on the second resultant structure, and the substrate is heated at a second temperature higher than the first temperature. The second capping layer suppresses a silicidation rate in the secondary heat treatment, thereby allowing a silicide of a good morphology to be achieved.

    摘要翻译： 提供了半导体器件制造方法。 在该方法中，在半导体衬底上形成栅极层并形成第一结构，在第一结果结构上形成金属层，在金属层上形成覆盖层，在金属层上形成金属硅化物 通过在第一温度下加热衬底，去除未反应的金属层和第一覆盖层以形成第二结构结构，在第二结构结构上形成第二覆盖层，并且将衬底在高于 第一个温度。 第二覆盖层抑制二次热处理中的硅化率，从而实现良好形态的硅化物。

    Method for fabricating MOS semiconductor device having salicide region and LDD structure
    22.
    发明授权
    Method for fabricating MOS semiconductor device having salicide region and LDD structure 有权
    制造具有硅化物区域和LDD结构的MOS半导体器件的方法

    公开(公告)号：US06255181B1

    公开(公告)日：2001-07-03

    申请号：US09161979

    申请日：1998-09-29

    申请人： Oh-Sung Song ,  Ja-Hum Ku

    发明人： Oh-Sung Song ,  Ja-Hum Ku

    IPC分类号： H01L21336

    CPC分类号： H01L29/665 ,  H01L21/2652 ,  H01L21/28518 ,  H01L29/6659

    摘要： A method for fabricating a MOS transistor involves forming a buffering layer on an active region, performing an ion implantation to form a heavily doped region (source/drain region), and forming a self-aligned silicide region (salicide region) on exposed silicon and polysilicon gate. With this method, a salicide region free from voids can be formed because transition metal material (for example, cobalt) and silicon atoms at an interface portion between the transition metal layer and the substrate silicon are not locally accelerated or delayed during the formation of the salicide region.

    摘要翻译： 制造MOS晶体管的方法包括在有源区上形成缓冲层，进行离子注入以形成重掺杂区（源极/漏极区），以及在暴露的硅上形成自对准的硅化物区（自对准硅化物区） 多晶硅门 通过这种方法，可以形成无空隙的自对准硅化物区域，因为过渡金属层和衬底硅之间的界面部分的过渡金属材料（例如钴）和硅原子在形成过程中不会局部加速或延迟 自杀地区。

    Methods of fabricating semiconductor device having a metal gate pattern
    24.
    发明申请
    Methods of fabricating semiconductor device having a metal gate pattern 有权
    制造具有金属栅极图案的半导体器件的方法

    公开(公告)号：US20090250752A1

    公开(公告)日：2009-10-08

    申请号：US12457323

    申请日：2009-06-08

    申请人： Ja-Hum Ku ,  Chang-Won Lee ,  Seong-Jun Heo ,  Sun-Pil Youn ,  Sung-Man Kim

    发明人： Ja-Hum Ku ,  Chang-Won Lee ,  Seong-Jun Heo ,  Sun-Pil Youn ,  Sung-Man Kim

    IPC分类号： H01L29/94 ,  H01L29/78

    CPC分类号： H01L21/823437 ,  H01L21/28247 ,  H01L29/4941 ,  H01L29/6656

    摘要： A method of fabricating a semiconductor device having a metal gate pattern is provided in which capping layers are used to control the relative oxidation rates of portions of the metal gate pattern during a oxidation process. The capping layer may be a multilayer structure and may be etched to form insulating spacers on the sidewalls of the metal gate pattern. The capping layer(s) allow the use of a selective oxidation process, which may be a wet oxidation process utilizing partial pressures of both H2O and H2 in an H2-rich atmosphere, to oxidize portions of the substrate and metal gate pattern while suppressing the oxidation of metal layers that may be included in the metal gate pattern. This allows etch damage to the silicon substrate and edges of the metal gate pattern to be reduced while substantially maintaining the original thickness of the gate insulating layer and the conductivity of the metal layer(s).

    摘要翻译： 提供一种制造具有金属栅极图案的半导体器件的方法，其中使用覆盖层来控制氧化过程中金属栅极图案的部分的相对氧化率。 覆盖层可以是多层结构，并且可以被蚀刻以在金属栅极图案的侧壁上形成绝缘间隔物。 封盖层允许使用选择性氧化工艺，其可以是在富H2气氛中使用H 2 O和H 2的分压的湿式氧化工艺，以氧化基板和金属栅极图案的部分，同时抑制 可以包括在金属栅极图案中的金属层的氧化。 这允许对硅衬底的蚀刻损伤和金属栅极图案的边缘减小，同时基本上保持栅极绝缘层的原始厚度和金属层的导电性。

    Methods of forming dual-damascene interconnect structures on semiconductor substrates using multiple planarization layers having different porosity characteristics
    28.
    发明申请
    Methods of forming dual-damascene interconnect structures on semiconductor substrates using multiple planarization layers having different porosity characteristics 有权
    使用具有不同孔隙率特性的多个平坦化层在半导体衬底上形成双镶嵌互连结构的方法

    公开(公告)号：US20070184649A1

    公开(公告)日：2007-08-09

    申请号：US11348428

    申请日：2006-02-06

    申请人： Kyoung-Woo Lee ,  Seung-Man Choi ,  Ja-Hum Ku ,  Ki-Chul Park ,  Sun Kim

    发明人： Kyoung-Woo Lee ,  Seung-Man Choi ,  Ja-Hum Ku ,  Ki-Chul Park ,  Sun Kim

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76808 ,  H01L21/31144

    摘要： Methods of forming integrated circuit devices include patterning an electrically insulating layer to support dual-damascene interconnect structures therein. The steps of patterning the electrically insulating layer include using multiple planarization layers having different porosity characteristics. Forming an interconnect structure within an integrated circuit device may include forming an electrically insulating layer on a substrate and forming at least one via hole extending at least partially through the electrically insulating layer. The at least one via hole is filled with a first electrically insulating material having a first porosity. The filled at least one via hole is then covered with a second electrically insulating material layer having a second porosity lower than the first porosity. The second electrically insulating material layer is selectively etched back to expose a first portion of the first electrically insulating material in the at least one via hole. The electrically insulating layer is selectively etched to define a trench therein that exposes a second portion of the first electrically insulating material in the at least one via hole. The first electrically insulating material, which has a relatively high degree of porosity, is then removed from the at least one via hole. This removal step may be performed using a relatively mild ashing process because of the high porosity of the first electrically insulating material.

    摘要翻译： 形成集成电路器件的方法包括图案化电绝缘层以支持其中的双镶嵌互连结构。 图案化电绝缘层的步骤包括使用具有不同孔隙特性的多个平坦化层。 在集成电路器件内形成互连结构可以包括在衬底上形成电绝缘层，并形成至少部分穿过电绝缘层延伸的至少一个通孔。 至少一个通孔填充有具有第一孔隙率的第一电绝缘材料。 填充的至少一个通孔然后被具有低于第一孔隙率的第二孔隙率的第二电绝缘材料层覆盖。 选择性地回蚀第二电绝缘材料层以暴露至少一个通孔中的第一电绝缘材料的第一部分。 电绝缘层被选择性蚀刻以在其中限定其中的沟槽，其暴露出至少一个通孔中的第一电绝缘材料的第二部分。 然后从该至少一个通孔去除具有较高孔隙率的第一电绝缘材料。 由于第一电绝缘材料的高孔隙率，该去除步骤可以使用相对温和的灰化过程进行。