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    Irregular Low Density Parity Check Decoder With Low Syndrome Error Handling
    23.
    发明申请
    Irregular Low Density Parity Check Decoder With Low Syndrome Error Handling 有权
    具有低综合征错误处理的不规则低密度奇偶校验解码器

    公开(公告)号：US20140168811A1

    公开(公告)日：2014-06-19

    申请号：US13777381

    申请日：2013-02-26

    Applicant: LSI CORPORATION

    Inventor： Shaohua Yang ,  Anatoli A. Bolotov ,  Chung-Li Wang ,  Zongwang Li ,  Shu Li ,  Mikhail I. Grinchuk

    IPC: H03M13/13 ,  G11B20/18

    CPC classification number: G11B20/18 ,  G11B20/1833 ,  G11B2020/185 ,  H03M13/09 ,  H03M13/1111 ,  H03M13/1128 ,  H03M13/27 ,  H03M13/6331

    Abstract: A data processing system is disclosed including a data decoder circuit, an error handling circuit and a syndrome checker circuit. The data decoder circuit is operable to apply a data decode algorithm to a decoder input to yield a decoded output, and to calculate a syndrome indicating an error level for the decoded output. The error handling circuit is operable to determine whether any errors in the decoded output involve user data bits. The syndrome checker circuit is operable to trigger the error handling circuit based at least in part on the syndrome.

    Abstract translation: 公开了一种数据处理系统，包括数据解码器电路，错误处理电路和综合检查电路。 数据解码器电路可操作以将数据解码算法应用于解码器输入以产生解码输出，并计算指示解码输出的误差电平的校正子。 错误处理电路可操作以确定解码输出中的任何错误是否涉及用户数据位。 综合征检查器电路可操作以至少部分地基于综合征来触发误差处理电路。

    Systems and methods for skip layer data decoding
    24.
    发明授权
    Systems and methods for skip layer data decoding 有权
    跳过层数据解码的系统和方法

    公开(公告)号：US09214959B2

    公开(公告)日：2015-12-15

    申请号：US13770008

    申请日：2013-02-19

    Applicant: LSI Corporation

    Inventor： Shaohua Yang ,  Fan Zhang ,  Chung-Li Wang ,  Shu Li

    IPC: H03M13/00 ,  H03M13/11 ,  G11B20/18

    CPC classification number: H03M13/1122 ,  G11B20/1833 ,  H03M13/1128 ,  H03M13/114 ,  H03M13/1142 ,  H03M13/6331 ,  H03M13/6343 ,  H03M13/658

    Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for performing data decoding including skipping one or more codeword blocks in the data decoding process. In one embodiment a data processing system includes a skip control circuit operable to skip re-application of a data decode algorithm to a portion of a codeword where at least the number of unsatisfied checks for the portion is zero.

    Abstract translation: 本发明涉及用于数据处理的系统和方法，更具体地涉及用于执行数据解码的系统和方法，包括在数据解码过程中跳过一个或多个码字块。 在一个实施例中，数据处理系统包括跳过控制电路，该跳过控制电路可操作以跳过将数据解码算法重新应用于代码字的至少部分的不满足检查数为零的部分。

    Min-sum based hybrid non-binary low density parity check decoder
    25.
    发明授权
    Min-sum based hybrid non-binary low density parity check decoder 有权
    基于最小和混合非二进制低密度奇偶校验解码器

    公开(公告)号：US09048874B2

    公开(公告)日：2015-06-02

    申请号：US13886103

    申请日：2013-05-02

    Applicant: LSI Corporation

    Inventor： Chung-Li Wang ,  Zongwang Li ,  Shu Li ,  Fan Zhang ,  Shaohua Yang

    IPC: H03M13/00 ,  H03M13/13 ,  H03M13/11

    CPC classification number: H03M13/13 ,  H03M13/1122 ,  H03M13/1125 ,  H03M13/1171 ,  H03M13/6583

    Abstract: An apparatus for decoding data includes a variable node processor, a check node processor, and a field transformation circuit. The variable node processor is operable to generate variable node to check node messages and to calculate perceived values based on check node to variable node messages. The check node processor is operable to generate the check node to variable node messages and to calculate checksums based on variable node to check node messages. The variable node processor and the check node processor comprise different Galois fields. The field transformation circuit is operable to transform the variable node to check node messages from a first of the different Galois fields to a second of the Galois fields.

    Abstract translation: 用于解码数据的装置包括可变节点处理器，校验节点处理器和场变换电路。 可变节点处理器可操作以生成变量节点以检查节点消息，并且基于校验节点到可变节点消息来计算感知值。 校验节点处理器可用于将校验节点生成到可变节点消息，并且基于变量节点来计算校验和以检查节点消息。 可变节点处理器和校验节点处理器包括不同的伽罗瓦域。 场变换电路可操作以将变量节点变换为将来自不同伽罗瓦域中的第一个的节点消息校验到伽罗瓦域中的第二个。

    Shift register-based layered low density parity check decoder
    26.
    发明授权
    Shift register-based layered low density parity check decoder 有权
    基于移位寄存器的分层低密度奇偶校验解码器

    公开(公告)号：US09048867B2

    公开(公告)日：2015-06-02

    申请号：US13898685

    申请日：2013-05-21

    Applicant: LSI Corporation

    Inventor： Dan Liu ,  Qi Zuo ,  Chung-Li Wang ,  Zongwang Li ,  Lei Wang

    IPC: H03M13/11 ,  H04L1/00

    CPC classification number: H03M13/1105 ,  H03M13/1114 ,  H03M13/1117 ,  H03M13/112 ,  H03M13/1122 ,  H03M13/1131 ,  H03M13/1137 ,  H03M13/114 ,  H03M13/116 ,  H03M13/1162 ,  H03M13/1171 ,  H03M13/1174 ,  H03M13/6331 ,  H03M13/6505 ,  H03M13/658 ,  H03M13/6583 ,  H04L1/005

    Abstract: An apparatus for layered low density parity check decoding includes a variable node processor and a check node processor. The variable node processor is operable to generate variable node to check node messages and to calculate perceived data values based on check node to variable node messages. The check node processor includes an intermediate message generator circuit operable to generate intermediate check node messages, a shift register based memory operable to store the intermediate check node messages, and at least one check node to variable node message generator circuit operable to generate the check node to variable node messages based on the intermediate check node messages from the shift register based memory.

    Abstract translation: 用于分层低密度奇偶校验解码的装置包括可变节点处理器和校验节点处理器。 可变节点处理器可操作以生成可变节点以检查节点消息，并且基于校验节点到可变节点消息来计算感知数据值。 校验节点处理器包括可操作以产生中间校验节点消息的中间消息发生器电路，可操作以存储中间校验节点消息的移位寄存器的存储器，以及至少一个校验节点，可变节点消息生成器电路可操作以生成校验节点 基于来自基于移位寄存器的存储器的中间检查节点消息到可变节点消息。

    Modified targeted symbol flipping for non-binary LDPC codes
    28.
    发明授权
    Modified targeted symbol flipping for non-binary LDPC codes 有权
    用于非二进制LDPC码的修改的目标符号翻转

    公开(公告)号：US08977926B2

    公开(公告)日：2015-03-10

    申请号：US13629726

    申请日：2012-09-28

    Applicant: LSI Corporation

    Inventor： Chung-Li Wang ,  Lei Chen ,  Fan Zhang ,  Shaohua Yang ,  Qi Qi

    IPC: H03M13/00 ,  G06F11/00 ,  H03M13/11 ,  H03M13/37

    CPC classification number: H03M13/1108 ,  H03M13/3738

    Abstract: A LDPC decoder includes a processor for targeted symbol flipping of suspicious bits in a LDPC codeword with unsatisfied checks. All combinations of check indices and variable indices are compiled and correlated into a pool of targeted symbol flipping candidates and returned along with symbol indices to a process that uses such symbol indices to identify symbols to flip in order to break a trapping set.

    Abstract translation: LDPC解码器包括用于不满足检查的LDPC码字中的可疑比特的目标符号翻转的处理器。 检查索引和可变索引的所有组合被编译并且相关联到目标符号翻转候选的池中，并且与符号索引一起返回到使用这样的符号索引来识别符号以便打破陷阱集合的过程。

    Shift Register-Based Layered Low Density Parity Check Decoder
    29.
    发明申请
    Shift Register-Based Layered Low Density Parity Check Decoder 有权
    基于移位寄存器的分层低密度奇偶校验解码器

    公开(公告)号：US20140351671A1

    公开(公告)日：2014-11-27

    申请号：US13898685

    申请日：2013-05-21

    Applicant: LSI Corporation

    Inventor： Dan Liu ,  Qi Zuo ,  Chung-Li Wang ,  Zongwang Li ,  Lei Wang

    IPC: H03M13/11

    CPC classification number: H03M13/1105 ,  H03M13/1114 ,  H03M13/1117 ,  H03M13/112 ,  H03M13/1122 ,  H03M13/1131 ,  H03M13/1137 ,  H03M13/114 ,  H03M13/116 ,  H03M13/1162 ,  H03M13/1171 ,  H03M13/1174 ,  H03M13/6331 ,  H03M13/6505 ,  H03M13/658 ,  H03M13/6583 ,  H04L1/005

    Abstract: An apparatus for layered low density parity check decoding includes a variable node processor and a check node processor. The variable node processor is operable to generate variable node to check node messages and to calculate perceived data values based on check node to variable node messages. The check node processor includes an intermediate message generator circuit operable to generate intermediate check node messages, a shift register based memory operable to store the intermediate check node messages, and at least one check node to variable node message generator circuit operable to generate the check node to variable node messages based on the intermediate check node messages from the shift register based memory.

    Abstract translation: 用于分层低密度奇偶校验解码的装置包括可变节点处理器和校验节点处理器。 可变节点处理器可操作以生成可变节点以检查节点消息，并且基于校验节点到可变节点消息来计算感知数据值。 校验节点处理器包括可操作以产生中间校验节点消息的中间消息发生器电路，可操作以存储中间校验节点消息的移位寄存器的存储器，以及至少一个校验节点，可变节点消息生成器电路可操作以生成校验节点 基于来自基于移位寄存器的存储器的中间检查节点消息到可变节点消息。

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