公开(公告)号：US08164141B2

公开(公告)日：2012-04-24

申请号：US12884198

申请日：2010-09-17

申请人： Po-Chao Tsao ,  Chang-Chi Huang ,  Ming-Tsung Chen ,  Feng-Yi Chang ,  Pei-Yu Chou ,  Jiunn-Hsiung Liao ,  Chih-Wen Feng ,  Ying-Chih Lin

发明人： Po-Chao Tsao ,  Chang-Chi Huang ,  Ming-Tsung Chen ,  Feng-Yi Chang ,  Pei-Yu Chou ,  Jiunn-Hsiung Liao ,  Chih-Wen Feng ,  Ying-Chih Lin

IPC分类号： H01L29/78

CPC分类号： H01L21/31144 ,  H01L21/76802 ,  H01L21/76831 ,  H01L23/485

摘要： An opening structure includes a semiconductor substrate, at least one dielectric layer disposed on the semiconductor substrate, wherein the dielectric layer has a plurality of openings exposing the semiconductor substrate, and each of the openings has a sidewall, a dielectric thin film covering at least a portion of the sidewall of each of the openings, and a metal layer filled in the openings.

摘要翻译： 开口结构包括半导体衬底，设置在半导体衬底上的至少一个电介质层，其中所述电介质层具有暴露所述半导体衬底的多个开口，并且每个所述开口具有侧壁，至少覆盖至少一个的电介质薄膜 每个开口的侧壁的一部分，以及填充在开口中的金属层。

公开(公告)号：US20120001338A1

公开(公告)日：2012-01-05

申请号：US13234159

申请日：2011-09-16

申请人： Po-Chao Tsao ,  Chang-Chi Huang ,  Ming-Tsung Chen ,  Feng-Yi Chang ,  Pei-Yu Chou ,  Jiunn-Hsiung Liao ,  Chih-Wen Feng ,  Ying-Chih Lin

发明人： Po-Chao Tsao ,  Chang-Chi Huang ,  Ming-Tsung Chen ,  Feng-Yi Chang ,  Pei-Yu Chou ,  Jiunn-Hsiung Liao ,  Chih-Wen Feng ,  Ying-Chih Lin

IPC分类号： H01L23/48

CPC分类号： H01L21/31144 ,  H01L21/76802 ,  H01L21/76831 ,  H01L23/485

摘要： An opening structure is disclosed. The opening structure includes: a semiconductor substrate; at least one dielectric layer disposed on the semiconductor substrate, wherein the dielectric layer has a plurality of openings exposing the semiconductor substrate, and each of the openings has a sidewall; a dielectric thin film covering at least a portion of the sidewall of each of the openings; an etch stop layer disposed between the semiconductor substrate and the dielectric layer and extending partially into the openings to isolate the dielectric thin film from the semiconductor substrate; and a metal layer filled in the openings.

摘要翻译： 公开了一种开口结构。 开口结构包括：半导体衬底; 设置在所述半导体衬底上的至少一个电介质层，其中所述电介质层具有暴露所述半导体衬底的多个开口，并且每个所述开口具有侧壁; 覆盖每个开口的侧壁的至少一部分的电介质薄膜; 蚀刻停止层，设置在所述半导体衬底和所述电介质层之间并且部分地延伸到所述开口中以将所述电介质薄膜与所述半导体衬底隔离; 以及填充在开口中的金属层。

公开(公告)号：US07572722B2

公开(公告)日：2009-08-11

申请号：US11685209

申请日：2007-03-13

申请人： Yi-Wei Chen ,  Chao-Ching Hsieh ,  Yi-Yiing Chiang ,  Tzung-Yu Hung ,  Yu-Lan Chang ,  Po-Chao Tsao ,  Chang-Chi Huang ,  Ming-Tsung Chen

发明人： Yi-Wei Chen ,  Chao-Ching Hsieh ,  Yi-Yiing Chiang ,  Tzung-Yu Hung ,  Yu-Lan Chang ,  Po-Chao Tsao ,  Chang-Chi Huang ,  Ming-Tsung Chen

IPC分类号： H01L21/3205

CPC分类号： H01L29/665 ,  H01L21/324 ,  H01L29/4933

摘要： A semiconductor device having nickel silicide and a method for fabricating nickel silicide. A semiconductor substrate having a plurality of doped regions is provided. Subsequently, a nickel layer is formed on the semiconductor substrate, and a first rapid thermal process (RTP) is performed to react the nickel layer with the doped regions disposed there under. Thereafter, the unreacted nickel layer is removed, and a second rapid thermal process is performed to form a semiconductor device having nickel silicide. The second rapid thermal process is a spike anneal process whose process temperature is between 400 and 600° C.

摘要翻译： 具有硅化镍的半导体器件和制造硅化镍的方法。 提供具有多个掺杂区域的半导体衬底。 随后，在半导体衬底上形成镍层，并进行第一快速热处理（RTP）以使镍层与设置在其下方的掺杂区域反应。 此后，除去未反应的镍层，进行第二快速热处理以形成具有硅化镍的半导体器件。 第二快速热处理是工艺温度在400和600℃之间的尖峰退火工艺。

公开(公告)号：US20070181955A1

公开(公告)日：2007-08-09

申请号：US11691485

申请日：2007-03-26

申请人： Ming-Tsung Chen ,  Chang-Chi Huang ,  Po-Chao Tsao

发明人： Ming-Tsung Chen ,  Chang-Chi Huang ,  Po-Chao Tsao

IPC分类号： H01L29/76

CPC分类号： H01L21/28518 ,  H01L21/26506 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/7834

摘要： A metal oxide semiconductor (MOS) transistor is disclosed. The MOS transistor includes: a semiconductor substrate; a gate disposed on the semiconductor substrate, wherein the gate comprises two sidewalls; a spacer formed on the sidewalls of the gate; a source/drain region disposed in the semiconductor substrate; a silicide layer disposed on top of the gate and the surface of the source/drain region; and a retarded interface layer disposed in the junction between the silicide layer and the gate and source/drain region.

摘要翻译： 公开了一种金属氧化物半导体（MOS）晶体管。 MOS晶体管包括：半导体衬底; 设置在所述半导体衬底上的栅极，其中所述栅极包括两个侧壁; 形成在栅极的侧壁上的间隔物; 设置在所述半导体衬底中的源/漏区; 设置在栅极的顶部和源极/漏极区域的表面上的硅化物层; 以及设置在硅化物层与栅极和源极/漏极区之间的结中的延迟界面层。

公开(公告)号：US20070063290A1

公开(公告)日：2007-03-22

申请号：US11162693

申请日：2005-09-20

申请人： Po-Chao Tsao ,  Chang-Chi Huang ,  Ming-Tsung Chen ,  Yi-Yiing Chiang ,  Yu-Lan Chang ,  Chung-Ju Lee ,  Chih-Ning Wu ,  Kuan-Yang Liao

发明人： Po-Chao Tsao ,  Chang-Chi Huang ,  Ming-Tsung Chen ,  Yi-Yiing Chiang ,  Yu-Lan Chang ,  Chung-Ju Lee ,  Chih-Ning Wu ,  Kuan-Yang Liao

IPC分类号： H01L29/76 ,  H01L21/336

CPC分类号： H01L29/6653 ,  H01L21/28518 ,  H01L21/31111 ,  H01L29/6659

摘要： A method for forming a metal oxide semiconductor (MOS) transistor is provided. First, a gate structure is formed over a substrate. Then, offset spacers are formed on respective sidewalls of the gate structure. A first ion implantation process is performed to form a lightly doped drain (LDD) in the substrate beside the gate structure. Other spacers are formed on respective sidewalls of the offset spacers. Thereafter, a second ion implantation process is performed to form source/drain region in the substrate beside the spacers. Then, a metal silicide layer is formed on the surface of the source and the drain. An oxide layer is formed on the surface of the metal silicide layer. The spacers are removed and an etching stop layer is formed on the substrate. With the oxide layer over the metal silicide layer, the solvent for removing the spacers is prevented from damaging the metal silicide layer.

摘要翻译： 提供一种用于形成金属氧化物半导体（MOS）晶体管的方法。 首先，在基板上形成栅极结构。 然后，在栅极结构的相应侧壁上形成偏移间隔物。 执行第一离子注入工艺以在栅极结构旁边的衬底中形成轻掺杂漏极（LDD）。 在偏置间隔物的相应侧壁上形成其它间隔物。 此后，进行第二离子注入工艺以在衬垫旁边的衬垫上形成源极/漏极区域。 然后，在源极和漏极的表面上形成金属硅化物层。 在金属硅化物层的表面上形成氧化物层。 去除间隔物，并在衬底上形成蚀刻停止层。 通过金属硅化物层上的氧化物层，可以防止用于除去间隔物的溶剂损坏金属硅化物层。

公开(公告)号：US07825034B2

公开(公告)日：2010-11-02

申请号：US11163149

申请日：2005-10-06

申请人： Po-Chao Tsao ,  Chang-Chi Huang ,  Ming-Tsung Chen

发明人： Po-Chao Tsao ,  Chang-Chi Huang ,  Ming-Tsung Chen

IPC分类号： H01L21/302

CPC分类号： H01L21/76802 ,  H01L21/76831

摘要： A substrate having an etch stop layer and at least a dielectric layer disposed from bottom to top is provided. The dielectric layer is then patterned to form a plurality of openings exposing the etch stop layer. A dielectric thin film is subsequently formed to cover the dielectric layer, the sidewalls of the openings, and the etch stop layer. The dielectric thin film disposed on the dielectric layer and the etch stop layer is then removed.

摘要翻译： 提供具有蚀刻停止层和至少从底部到顶部设置的电介质层的衬底。 然后将电介质层图案化以形成露出蚀刻停止层的多个开口。 随后形成介电薄膜以覆盖电介质层，开口的侧壁和蚀刻停止层。 然后去除设置在电介质层和蚀刻停止层上的电介质薄膜。

公开(公告)号：US07759742B2

公开(公告)日：2010-07-20

申请号：US11691485

申请日：2007-03-26

申请人： Ming-Tsung Chen ,  Chang-Chi Huang ,  Po-Chao Tsao

发明人： Ming-Tsung Chen ,  Chang-Chi Huang ,  Po-Chao Tsao

IPC分类号： H01L29/76

CPC分类号： H01L21/28518 ,  H01L21/26506 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/7834

摘要： A metal oxide semiconductor (MOS) transistor is disclosed. The MOS transistor includes: a semiconductor substrate; a gate disposed on the semiconductor substrate, wherein the gate comprises two sidewalls; a spacer formed on the sidewalls of the gate; a source/drain region disposed in the semiconductor substrate; a silicide layer disposed on top of the gate and the surface of the source/drain region; and a retarded interface layer disposed in the junction between the silicide layer and the gate and source/drain region.

摘要翻译： 公开了一种金属氧化物半导体（MOS）晶体管。 MOS晶体管包括：半导体衬底; 设置在所述半导体衬底上的栅极，其中所述栅极包括两个侧壁; 形成在栅极的侧壁上的间隔物; 设置在所述半导体衬底中的源/漏区; 设置在栅极的顶部和源极/漏极区域的表面上的硅化物层; 以及设置在硅化物层与栅极和源极/漏极区之间的结中的延迟界面层。

公开(公告)号：US09136348B2

公开(公告)日：2015-09-15

申请号：US13417337

申请日：2012-03-12

申请人： Ming-Te Wei ,  Shin-Chuan Huang ,  Yu-Hsiang Hung ,  Po-Chao Tsao ,  Chia-Jui Liang ,  Ming-Tsung Chen ,  Chia-Wen Liang

发明人： Ming-Te Wei ,  Shin-Chuan Huang ,  Yu-Hsiang Hung ,  Po-Chao Tsao ,  Chia-Jui Liang ,  Ming-Tsung Chen ,  Chia-Wen Liang

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L29/165

CPC分类号： H01L29/66492 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

摘要： A semiconductor structure includes a gate structure disposed on a substrate and having an outer spacer, a recess disposed in the substrate and adjacent to the gate structure, a doped epitaxial material filling up the recess, a cap layer including an undoped epitaxial material and disposed on the doped epitaxial material, a lightly doped drain disposed below the cap layer and sandwiched between the doped epitaxial material and the cap layer, and a silicide disposed on the cap layer and covering the doped epitaxial material to cover the cap layer together with the outer spacer without directly contacting the lightly doped drain.

摘要翻译： 半导体结构包括设置在基板上并具有外部间隔件的栅极结构，设置在基板中并与栅极结构相邻的凹槽，填充凹部的掺杂的外延材料，包括未掺杂的外延材料的盖层， 所述掺杂的外延材料是设置在所述覆盖层下方并且夹在所述掺杂的外延材料和所述覆盖层之间的轻掺杂漏极，以及设置在所述覆盖层上并覆盖所述掺杂外延材料以与所述外部间隔物一起覆盖所述覆盖层的硅化物 而不直接接触轻掺杂的漏极。

公开(公告)号：US20130234261A1

公开(公告)日：2013-09-12

申请号：US13417337

申请日：2012-03-12

申请人： Ming-Te Wei ,  Shin-Chuan Huang ,  Yu-Hsiang Hung ,  Po-Chao Tsao ,  Chia-Jui Liang ,  Ming-Tsung Chen ,  Chia-Wen Liang

发明人： Ming-Te Wei ,  Shin-Chuan Huang ,  Yu-Hsiang Hung ,  Po-Chao Tsao ,  Chia-Jui Liang ,  Ming-Tsung Chen ,  Chia-Wen Liang

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66492 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

摘要： A semiconductor structure includes a gate structure disposed on a substrate and having an outer spacer, a recess disposed in the substrate and adjacent to the gate structure, a doped epitaxial material filling up the recess, a cap layer including an undoped epitaxial material and disposed on the doped epitaxial material, a lightly doped drain disposed below the cap layer and sandwiched between the doped epitaxial material and the cap layer, and a silicide disposed on the cap layer and covering the doped epitaxial material to cover the cap layer together with the outer spacer without directly contacting the lightly doped drain.

公开(公告)号：US20110006437A1

公开(公告)日：2011-01-13

申请号：US12884198

申请日：2010-09-17

申请人： Po-Chao Tsao ,  Chang-Chi Huang ,  Ming-Tsung Chen ,  Feng-Yi Chang ,  Pei-Yu Chou ,  Jiunn-Hsiung Liao ,  Chih-Wen Feng ,  Ying-Chih Lin

发明人： Po-Chao Tsao ,  Chang-Chi Huang ,  Ming-Tsung Chen ,  Feng-Yi Chang ,  Pei-Yu Chou ,  Jiunn-Hsiung Liao ,  Chih-Wen Feng ,  Ying-Chih Lin

IPC分类号： H01L23/48

CPC分类号： H01L21/31144 ,  H01L21/76802 ,  H01L21/76831 ,  H01L23/485

摘要： An opening structure includes a semiconductor substrate, at least one dielectric layer disposed on the semiconductor substrate, wherein the dielectric layer has a plurality of openings exposing the semiconductor substrate, and each of the openings has a sidewall, a dielectric thin film covering at least a portion of the sidewall of each of the openings, and a metal layer filled in the openings.

摘要翻译： 开口结构包括半导体衬底，设置在半导体衬底上的至少一个电介质层，其中所述电介质层具有暴露所述半导体衬底的多个开口，并且每个所述开口具有侧壁，至少覆盖至少一个的电介质薄膜 每个开口的侧壁的一部分，以及填充在开口中的金属层。