公开(公告)号：US20070141731A1

公开(公告)日：2007-06-21

申请号：US11316108

申请日：2005-12-20

申请人： Gerrit Hemink ,  Loc Tu ,  Jian Chen ,  Kiran Ponnuru

发明人： Gerrit Hemink ,  Loc Tu ,  Jian Chen ,  Kiran Ponnuru

IPC分类号： H01L21/66 ,  G01R31/26

CPC分类号： G11C29/50 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/04 ,  G11C16/0483 ,  G11C16/349 ,  G11C29/50004 ,  G11C29/52

摘要： Future operability predictor testing is incorporated into the fabrication of integrated circuits that utilize redundancy. Select reliability testing can be used to identify circuit elements such as memory cells that fail or become defective over time. Future operability tests and associated stress conditions are then developed for application during the fabrication process to identify memory cells that may pose a future operability concern before they actually fail. Memory cells that are determined to pose a future operability concern are replaced by redundant memory cells.

摘要翻译： 未来的可操作性预测器测试被并入利用冗余的集成电路的制造中。 选择可靠性测试可用于识别诸如存储器单元之类的电路元件，这些元件失效或随时间变得有缺陷。 然后开发未来的可操作性测试和相关的应力条件，以便在制造过程中应用以识别在实际失效之前可能构成未来可操作性问题的存储器单元。 被确定为构成未来可操作性问题的存储器单元被冗余存储器单元替代。

公开(公告)号：US20080311684A1

公开(公告)日：2008-12-18

申请号：US11763287

申请日：2007-06-14

申请人： Loc Tu ,  Jian Chen ,  Alex Mak ,  Tien-chien Kuo ,  Long Pham

发明人： Loc Tu ,  Jian Chen ,  Alex Mak ,  Tien-chien Kuo ,  Long Pham

IPC分类号： H01L21/66

CPC分类号： H01L22/20 ,  H01L27/108 ,  H01L27/11 ,  H01L27/115 ,  H01L27/11524

摘要： Memory die are provided with programmable chip enable circuitry to allow particular memory die to be disabled after packaging and/or programmable chip address circuitry to allow particular memory die to be readdressed after being packaged. In a multi-chip memory package, a memory die that fails package-level testing can be disabled and isolated from the memory package by a programmable circuit that overrides the master chip enable signal received from the controller or host device. To provide a continuous address range, one or more of the non-defective memory die can be re-addressed using another programmable circuit that replaces the unique chip address provided by the pad bonding. Memory chips can also be also be readdressed after packaging independently of detecting a failed memory die.

摘要翻译： 存储器管芯具有可编程芯片使能电路，以允许在封装和/或可编程芯片地址电路之后禁止特定存储器管芯，以允许特定存储器管芯在封装之后被读取。 在多芯片存储器封装中，可以通过可覆盖从控制器或主机设备接收的主芯片使能信号的可编程电路来禁止与存储器封装隔离的封装级测试失败的存储器管芯。 为了提供连续的地址范围，可以使用替代由焊盘键合提供的唯一芯片地址的另一个可编程电路来重新寻址无缺陷存储器管芯中的一个或多个。 封装后的存储器芯片也可以被独立于检测出错的存储器芯片而被读取。

公开(公告)号：US07457178B2

公开(公告)日：2008-11-25

申请号：US11331479

申请日：2006-01-12

申请人： Loc Tu ,  Jeffrey Lutze ,  Jun Wan ,  Jian Chen

发明人： Loc Tu ,  Jeffrey Lutze ,  Jun Wan ,  Jian Chen

IPC分类号： G11C29/00

CPC分类号： G11C16/30 ,  G11C11/5628 ,  G11C16/04 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028

摘要： A flash memory device of the multi-level cell (MLC) type, in which control gate voltages in read and programming operations and a bandgap reference voltage source are trimmable from external terminals, is disclosed. In a special test mode, control gate voltages can be applied to a selected programmed memory cell so that the threshold voltage of the cell can be sensed. A digital-to-analog converter (DAC) use for programming and a second read/verify DAC apply varying analog voltages and are sequentially used to verify the programming of an associated set of memory cells in this special test mode, with the DAC input values that provide the closest result selected for use in normal operation. These DAC's are dependent on the value of a reference source that my also be trimmed.

摘要翻译： 公开了一种多电平单元（MLC）类型的闪速存储器件，其中读取和编程操作中的控制栅极电压和带隙基准电压源可从外部端子进行调节。 在特殊测试模式中，可以将控制栅极电压施加到所选择的编程存储单元，从而可以感测单元的阈值电压。 用于编程的数/模转换器（DAC）和第二读/验用DAC应用变化的模拟电压，并且在该特殊测试模式下依次用于验证相关联的存储器单元的编程，DAC输入值 它提供了选择用于正常操作的最接近的结果。 这些DAC取决于我也被修剪的参考源的值。

公开(公告)号：US20070159888A1

公开(公告)日：2007-07-12

申请号：US11332567

申请日：2006-01-12

申请人： Loc Tu ,  Jeffrey Lutze ,  Jun Wan ,  Jian Chen

发明人： Loc Tu ,  Jeffrey Lutze ,  Jun Wan ,  Jian Chen

IPC分类号： G11C16/06

CPC分类号： G11C16/0483 ,  G11C7/16 ,  G11C11/5628 ,  G11C16/04 ,  G11C16/12 ,  G11C16/3454 ,  G11C16/3459 ,  G11C27/005 ,  G11C29/028 ,  G11C29/48 ,  G11C29/50 ,  G11C29/50004 ,  G11C2029/5004 ,  G11C2211/5621 ,  G11C2211/5634

摘要： A flash memory device of the multi-level cell (MLC) type, in which control gate voltages in read and programming operations and a bandgap reference voltage source are trimmable from external terminals, is disclosed. In a special test mode, control gate voltages can be applied to a selected programmed memory cell so that the threshold voltage of the cell can be sensed. A digital-to-analog converter (DAC) use for programming and a second read/verify DAC apply varying analog voltages and are sequentially used to verify the programming of an associated set of memory cells in this special test mode, with the DAC input values that provide the closest result selected for use in normal operation. These DAC's are dependent on the value of a reference source that my also be trimmed.

摘要翻译： 公开了一种多电平单元（MLC）类型的闪速存储器件，其中读取和编程操作中的控制栅极电压和带隙基准电压源可从外部端子进行调节。 在特殊测试模式中，可以将控制栅极电压施加到所选择的编程存储单元，从而可以感测单元的阈值电压。 用于编程的数/模转换器（DAC）和第二读/验用DAC应用变化的模拟电压，并且在该特殊测试模式下依次用于验证相关联的存储器单元的编程，DAC输入值 它提供了选择用于正常操作的最接近的结果。 这些DAC取决于我也被修剪的参考源的值。

公开(公告)号：US20050094440A1

公开(公告)日：2005-05-05

申请号：US11003545

申请日：2004-12-03

申请人： Loc Tu ,  Jian Chen

发明人： Loc Tu ,  Jian Chen

IPC分类号： G11C29/50 ,  G11C11/34

CPC分类号： G11C29/50

摘要： An error recovery technique is used on marginal nonvolatile memory cells. A marginal memory cell is unreadable because it has a voltage threshold (VT) of less than zero volts. By biasing adjacent memory cells, this will shift the voltage threshold of the marginal memory cells, so that it is a positive value. Then the VT of the marginal memory cell can be determined. The technique is applicable to both binary and multistate memory cells.

摘要翻译： 在边缘非易失性存储器单元上使用错误恢复技术。 边缘存储器单元是不可读的，因为它具有小于零伏特的电压阈值（VT）。 通过偏置相邻的存储单元，这将移位边际存储单元的电压阈值，使其为正值。 然后可以确定边缘记忆单元的VT。 该技术适用于二进制和多状态存储器单元。

公开(公告)号：US07715255B2

公开(公告)日：2010-05-11

申请号：US11763287

申请日：2007-06-14

申请人： Loc Tu ,  Jian Chen ,  Alex Mak ,  Tien-Chien Kuo ,  Long Pham

发明人： Loc Tu ,  Jian Chen ,  Alex Mak ,  Tien-Chien Kuo ,  Long Pham

IPC分类号： G11C7/00

CPC分类号： H01L22/20 ,  H01L27/108 ,  H01L27/11 ,  H01L27/115 ,  H01L27/11524

摘要： Memory die are provided with programmable chip enable circuitry to allow particular memory die to be disabled after packaging and/or programmable chip address circuitry to allow particular memory die to be readdressed after being packaged. In a multi-chip memory package, a memory die that fails package-level testing can be disabled and isolated from the memory package by a programmable circuit that overrides the master chip enable signal received from the controller or host device. To provide a continuous address range, one or more of the non-defective memory die can be readdressed using another programmable circuit that replaces the unique chip address provided by the pad bonding. Memory chips can also be also be readdressed after packaging independently of detecting a failed memory die.

摘要翻译： 存储器管芯具有可编程芯片使能电路，以允许在封装和/或可编程芯片地址电路之后禁止特定存储器管芯，以允许特定存储器管芯在封装之后被读取。 在多芯片存储器封装中，可以通过可覆盖从控制器或主机设备接收的主芯片使能信号的可编程电路来禁止与存储器封装隔离的封装级测试失败的存储器管芯。 为了提供连续的地址范围，可以使用另一个可替代由焊盘键合提供的唯一芯片地址的可编程电路来读取一个或多个无缺陷存储器管芯。 封装后的存储器芯片也可以被独立于检测出错的存储器芯片而被读取。

公开(公告)号：US07561482B2

公开(公告)日：2009-07-14

申请号：US11470945

申请日：2006-09-07

申请人： Loc Tu ,  Wangang Tsai

发明人： Loc Tu ,  Wangang Tsai

IPC分类号： G11C29/00 ,  G11C7/00

CPC分类号： G11C29/76 ,  G11C29/82

摘要： A method and apparatus provide an improved identification and isolation of defective blocks in non-volatile memory devices having a plurality of user accessible blocks of non-volatile storage elements where each block also has an associated defective block latch. The method provides for sensing each defective block latch to determine whether the defective block latch was set due to a defect, and storing, in temporary on chip memory, address data corresponding to each set latch. The method further involves retrieving the address data and disabling defective blocks based upon the address data. A non-volatile memory device is also described having a controller which senses the defective block latches, stores address data for each block having a set latch, and subsequently retrieves the stored address data to set the defective block latches based upon the address data.

摘要翻译： 方法和装置提供了具有多个非易失性存储元件的多个用户可访问块的非易失性存储器件中的缺陷块的改进的识别和隔离，其中每个块还具有相关联的缺陷块锁存器。 该方法提供了感测每个缺陷块锁存器以确定由于缺陷而是否设置了缺陷块锁存器，并且在临时片上存储器中存储与每个锁存器对应的地址数据。 该方法还包括基于地址数据检索地址数据和禁用缺陷块。 还描述了一种非易失性存储器件，其具有感测缺陷块锁存器的控制器，存储具有设置锁存器的每个块的地址数据，并且随后检索存储的地址数据，以基于地址数据设置缺陷块锁存器。