公开(公告)号：US20070141731A1

公开(公告)日：2007-06-21

申请号：US11316108

申请日：2005-12-20

申请人： Gerrit Hemink ,  Loc Tu ,  Jian Chen ,  Kiran Ponnuru

发明人： Gerrit Hemink ,  Loc Tu ,  Jian Chen ,  Kiran Ponnuru

IPC分类号： H01L21/66 ,  G01R31/26

CPC分类号： G11C29/50 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/04 ,  G11C16/0483 ,  G11C16/349 ,  G11C29/50004 ,  G11C29/52

摘要： Future operability predictor testing is incorporated into the fabrication of integrated circuits that utilize redundancy. Select reliability testing can be used to identify circuit elements such as memory cells that fail or become defective over time. Future operability tests and associated stress conditions are then developed for application during the fabrication process to identify memory cells that may pose a future operability concern before they actually fail. Memory cells that are determined to pose a future operability concern are replaced by redundant memory cells.

摘要翻译： 未来的可操作性预测器测试被并入利用冗余的集成电路的制造中。 选择可靠性测试可用于识别诸如存储器单元之类的电路元件，这些元件失效或随时间变得有缺陷。 然后开发未来的可操作性测试和相关的应力条件，以便在制造过程中应用以识别在实际失效之前可能构成未来可操作性问题的存储器单元。 被确定为构成未来可操作性问题的存储器单元被冗余存储器单元替代。

公开(公告)号：US20080019180A1

公开(公告)日：2008-01-24

申请号：US11866261

申请日：2007-10-02

申请人： Jun Wan ,  Jeffrey Lutze ,  Masaaki Higashitani ,  Gerrit Hemink ,  Ken Oowada ,  Jian Chen ,  Geoffrey Gongwer

发明人： Jun Wan ,  Jeffrey Lutze ,  Masaaki Higashitani ,  Gerrit Hemink ,  Ken Oowada ,  Jian Chen ,  Geoffrey Gongwer

IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C16/06

CPC分类号： G11C16/3418

摘要： A non-volatile memory system is programmed so as to reduce or avoid program disturb. In accordance with one embodiment, multiple program inhibit schemes are employed for a single non-volatile memory system. Program inhibit schemes are selected based on the word line being programmed. Certain program inhibit schemes have been discovered to better minimize or eliminate program disturb at select word lines. In one embodiment, selecting a program inhibit scheme includes selecting a program voltage pulse ramp rate. Different ramp rates have been discovered to better minimize program disturb when applied to select word lines. In another embodiment, the temperature of a memory system is detected before or during a program operation. A program inhibit scheme can be selected based on the temperature of the system.

摘要翻译： 编程非易失性存储器系统以减少或避免编程干扰。 根据一个实施例，对于单个非易失性存储器系统采用多个程序禁止方案。 基于正在编程的字线选择程序禁止方案。 已经发现某些程序禁止方案能够更好地最小化或消除选择字线上的程序干扰。 在一个实施例中，选择编程禁止方案包括选择编程电压脉冲斜率。 在应用于选择字线时，已经发现了不同的斜率以更好地最小化程序干扰。 在另一个实施例中，在程序操作之前或期间检测存储器系统的温度。 可以基于系统的温度来选择程序禁止方案。

公开(公告)号：US20060279990A1

公开(公告)日：2006-12-14

申请号：US11127743

申请日：2005-05-12

申请人： Jun Wan ,  Jeffrey Lutze ,  Masaaki Higashitani ,  Gerrit Hemink ,  Ken Oowada ,  Jian Chen ,  Geoffrey Gongwer

发明人： Jun Wan ,  Jeffrey Lutze ,  Masaaki Higashitani ,  Gerrit Hemink ,  Ken Oowada ,  Jian Chen ,  Geoffrey Gongwer

IPC分类号： G11C16/04

CPC分类号： G11C16/3418

摘要： A non-volatile memory system is programmed so as to reduce or avoid program disturb. In accordance with one embodiment, multiple program inhibit schemes are employed for a single non-volatile memory system. Program inhibit schemes are selected based on the word line being programmed. Certain program inhibit schemes have been discovered to better minimize or eliminate program disturb at select word lines. In one embodiment, selecting a program inhibit scheme includes selecting a program voltage pulse ramp rate. Different ramp rates have been discovered to better minimize program disturb when applied to select word lines. In another embodiment, the temperature of a memory system is detected before or during a program operation. A program inhibit scheme can be selected based on the temperature of the system.

摘要翻译： 编程非易失性存储器系统以减少或避免编程干扰。 根据一个实施例，对于单个非易失性存储器系统采用多个程序禁止方案。 基于正在编程的字线选择程序禁止方案。 已经发现某些程序禁止方案能够更好地最小化或消除选择字线上的程序干扰。 在一个实施例中，选择编程禁止方案包括选择编程电压脉冲斜率。 在应用于选择字线时，已经发现了不同的斜率以更好地最小化程序干扰。 在另一个实施例中，在程序操作之前或期间检测存储器系统的温度。 可以基于系统的温度来选择程序禁止方案。

公开(公告)号：US20060221683A1

公开(公告)日：2006-10-05

申请号：US11099239

申请日：2005-04-05

申请人： Jian Chen ,  Raul-Adrian Cernea ,  Gerrit Hemink

发明人： Jian Chen ,  Raul-Adrian Cernea ,  Gerrit Hemink

IPC分类号： G11C16/04

CPC分类号： G11C11/5642 ,  G11C11/5628 ,  G11C16/26 ,  G11C16/3418 ,  G11C16/3422 ,  G11C16/3431

摘要： Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other adjacent charge storing elements). The problem occurs most pronouncedly between sets of adjacent memory cells that have been programmed at different times. To compensate for this coupling, the read process for a given memory cell will take into account the programmed state of an adjacent memory cell.

摘要翻译： 存在于非易失性存储单元的浮动栅极（或其他电荷存储元件）上的表观电荷的变化可能发生，因为基于存储在相邻浮动栅极（或其它相邻电荷存储元件）中的电荷的电场的耦合 ）。 在不同时间编程的相邻存储器单元组之间最明显地出现该问题。 为了补偿该耦合，给定存储器单元的读取过程将考虑相邻存储器单元的编程状态。

公开(公告)号：US20070242524A1

公开(公告)日：2007-10-18

申请号：US11414758

申请日：2006-04-28

申请人： Gerrit Hemink

发明人： Gerrit Hemink

IPC分类号： G11C16/04 ,  G11C11/34

CPC分类号： G11C11/5628 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3427 ,  G11C2211/5621

摘要： The unintentional programming of an unselected (or inhibited) non-volatile storage element during a program operation that intends to program another non-volatile storage element is referred to as “program disturb.” A system is proposed for programming and/or reading non-volatile storage that reduces the effect of program disturb. In one embodiment, different verify levels are used for a particular word line (or other grouping of storage elements) during a programming process. In another embodiment, different compare levels are used for a particular word (or other grouping of storage elements) during a read process.

摘要翻译： 在编程操作期间，未编程（或禁止）非易失性存储元件意图编程另一非易失性存储元件的无意编程被称为“程序干扰”。 提出了一种用于编程和/或读取非易失性存储器的系统，其减少了编程干扰的影响。 在一个实施例中，在编程过程期间，对于特定字线（或存储元件的其他分组）使用不同的验证电平。 在另一个实施例中，在读取过程期间，不同的比较级别用于特定单词（或存储单元的其他分组）。

公开(公告)号：US20050174852A1

公开(公告)日：2005-08-11

申请号：US10774014

申请日：2004-02-06

申请人： Gerrit Hemink

发明人： Gerrit Hemink

IPC分类号： G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  G11C11/34

CPC分类号： G11C16/10 ,  G11C16/0483

摘要： A low voltage of the order of or one to three volts instead of an intermediate VPASS voltage (e.g. of the order of five to ten volts) is applied to word line zero immediately adjacent to the source or drain side select gate of a NAND flash device to reduce or prevent the shifting of threshold voltage of the memory cells coupled to word line zero during the programming cycles of the different cells of the NAND strings. This may be implemented in any one of a variety of different self boosting schemes including erased areas self boosting and local self boosting schemes. In a modified erased area self boosting scheme, low voltages are applied to two or more word lines on the source side of the selected word line to reduce band-to-band tunneling and to improve the isolation between two boosted channel regions. In a modified local self boosting scheme, zero volt or low voltages are applied to two or more word lines on the source side and to two or more word lines on the drain side of the selected word line to reduce band-to-band tunneling and to improve the isolation of the channel areas coupled to the selected word line.

摘要翻译： 代替中间VASS PASS电压（例如5到10伏特的数量级）的一级或一到三伏的低电压被施加到紧邻源极或漏极的字线零点 NAND闪存器件的侧选择栅极，以在NAND串的不同单元的编程周期期间减少或防止耦合到字线零的存储器单元的阈值电压偏移。 这可以在各种不同的自增强方案中的任何一种中实现，包括擦除区域自增强和局部自增强方案。 在修改的擦除区域自增强方案中，将低电压施加到所选字线的源极侧上的两个或更多个字线，以减少带间隧穿并改善两个增强的通道区域之间的隔离。 在修改后的局部自增强方案中，将零电压或低电压施加到源极侧的两条或更多条字线和所选择的字线的漏极侧上的两条或多条字线，以减少带间隧穿和 以改善耦合到所选字线的通道区域的隔离。

公开(公告)号：US20070171719A1

公开(公告)日：2007-07-26

申请号：US11313023

申请日：2005-12-19

申请人： Gerrit Hemink ,  Ken Oowada

发明人： Gerrit Hemink ,  Ken Oowada

IPC分类号： G11C16/04

CPC分类号： G11C16/12 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3459 ,  G11C2211/5621

摘要： Non-volatile storage elements are programmed in a manner that reduces program disturb by using modified pass voltages. -In particular, during the programming of a selected storage element associated with a selected word line, a higher pass voltage is applied to word lines associated with previously programmed non-volatile storage elements in the set than to word lines associated with unprogrammed and/or partly programmed non-volatile storage elements in the set. The pass voltage is sufficiently high to balance the channel potentials on the source and drain sides of the selected word line and/or to reduce leakage of charge between the boosted channel regions. Optionally, an isolation region is formed between the boosted channel regions by applying a reduced voltage on one or more word lines between the selected word line and the word lines that receive the higher pass voltage.

摘要翻译： 非易失性存储元件以通过使用修改的通过电压来减少编程干扰的方式进行编程。 特别地，在与所选择的字线相关联的所选择的存储元件的编程期间，将较高的通过电压施加到与组中的先前编程的非易失性存储元件相关联的字线，而不是与未编程的和/或 该组中部分编程的非易失性存储元件。 通过电压足够高以平衡所选字线的源极和漏极侧上的沟道电位和/或减小在升压的沟道区之间的电荷泄漏。 可选地，通过在所选择的字线和接收较高通过电压的字线之间的一个或多个字线上施加降低的电压，在升压的沟道区之间形成隔离区。

公开(公告)号：US20070147118A1

公开(公告)日：2007-06-28

申请号：US11319260

申请日：2005-12-27

申请人： Tuan Pham ,  Masaaki Higashitani ,  Hao Fang ,  Gerrit Hemink

发明人： Tuan Pham ,  Masaaki Higashitani ,  Hao Fang ,  Gerrit Hemink

IPC分类号： G11C16/04 ,  G11C11/34 ,  G11C16/06

CPC分类号： G11C16/0483 ,  H01L23/5222 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11534 ,  H01L2924/0002 ,  H01L2924/00

摘要： A NAND flash memory device incorporates a unique booster plate design. The booster plate is biased during read and program operations and the coupling to the floating gates in many cases reduces the voltage levels necessary to program and read the charge stored in the gates. The booster plate also shields against unwanted coupling between floating gates. Self boosting, local self boosting, and erase area self boosting modes used with the unique booster plate further improve read/write reliability and accuracy. A more compact and reliable memory device can hence be realized according to the present invention.

摘要翻译： NAND闪存器件采用独特的增压板设计。 升压板在读取和编程操作期间被偏置，并且在许多情况下与浮动栅极的耦合降低了编程和读取存储在栅极中的电荷所需的电压电平。 升压板还屏蔽浮动栅极之间的不必要的耦合。 自升压，局部自升压，以及独特升压板使用的擦除区域自升压模式，进一步提高了读/写可靠性和精度。 因此，根据本发明可以实现更紧凑和可靠的存储器件。

公开(公告)号：US20060104120A1

公开(公告)日：2006-05-18

申请号：US10990702

申请日：2004-11-16

申请人： Gerrit Hemink

发明人： Gerrit Hemink

IPC分类号： G11C16/04

CPC分类号： G11C11/5628 ,  G11C16/10 ,  G11C16/3468 ,  G11C16/3486 ,  G11C2216/14

摘要： A program pulse is applied to a set of non-volatile storage elements. The magnitude of the program pulse is chosen to be low enough such that no non-volatile storage elements will be over programmed. The non-volatile storage elements are tested to determine whether at least one non-volatile storage element (or some other minimum number) has been programmed past a test threshold. If so, the set of non-volatile memory elements is considered to have one or more fast programming non-volatile storage elements and future programming is performed using a smaller increment value for subsequent program pulses. If the set of non-volatile memory elements is not determined to have one or more fast programming non-volatile storage elements, then a larger increment value is used for subsequent program pulses until one non-volatile storage element (or some other minimum number) has been programmed past the test threshold, at which point the smaller increment value is used for subsequent program pulses.

公开(公告)号：US20080019164A1

公开(公告)日：2008-01-24

申请号：US11773927

申请日：2007-07-05

申请人： Gerrit Hemink ,  Teruhiko Kamei

发明人： Gerrit Hemink ,  Teruhiko Kamei

IPC分类号： G11C17/00

CPC分类号： G11C16/344 ,  G11C11/5635 ,  G11C16/0483 ,  G11C16/16 ,  G11C16/3404 ,  G11C16/3445 ,  G11C2211/5621

摘要： The erase voltage applied to a set of non-volatile storage elements being erased is structured to provide controlled shifts in the threshold voltage of the storage elements. The erase voltage is applied as a series of voltage pulses, when necessary, to shift the threshold voltage of to-be-erased memory cells below a verify level indicative of an erased condition. To avoid over-erasing the memory cells, the second erase voltage pulse is decreased, or not increased, in magnitude when compared to the previously applied voltage pulse. By decreasing or not increasing the size of the erase voltage, the amount of charge transferred from the cells by the second pulse is controlled to more accurately position an erased threshold voltage distribution for the cells near the verify level. Subsequent erase voltage pulses are increased in magnitude to provide further erasing when needed.

摘要翻译： 施加到被擦除的一组非易失性存储元件的擦除电压被构造成提供存储元件的阈值电压的受控偏移。 当需要时，将擦除电压作为一系列电压脉冲施加以将被擦除的存储器单元的阈值电压移动到指示擦除状态的验证电平以下。 为了避免过度擦除存储单元，与先前施加的电压脉冲相比，第二擦除电压脉冲的幅度减小或不增加。 通过减小或不增加擦除电压的大小，控制从单元传输的第二脉冲的电荷量，以更准确地定位靠近验证电平的单元的擦除的阈值电压分布。 随后的擦除电压脉冲的幅度增大，以便在需要时进一步擦除。