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41 条记录 (耗时 0.018 秒)

    Triple-gate transistor with reverse shallow trench isolation
    21.
    发明授权
    Triple-gate transistor with reverse shallow trench isolation 有权
    具有反向浅沟槽隔离的三栅极晶体管

    公开(公告)号：US08389391B2

    公开(公告)日：2013-03-05

    申请号：US12696616

    申请日：2010-01-29

    申请人： James J. Chambers ,  Mark R. Visokay

    发明人： James J. Chambers ,  Mark R. Visokay

    IPC分类号： H01L21/3205

    CPC分类号： H01L29/7851 ,  H01L29/66795

    摘要： Example embodiments provide triple-gate semiconductor devices isolated by reverse shallow trench isolation (STI) structures and methods for their manufacture. In an example process, stacked layers including a form layer over a dielectric layer can be formed over a semiconductor substrate. One or more trenches can be formed by etching through the stacked layers. The one or more trenches can be filled by an active area material to form one or more active areas, which can be isolated by remaining portions of the dielectric layer. Bodies of the active area material can be exposed by removing the form layer. One or more triple-gate devices can then be formed on the exposed active area material. The example triple-gate semiconductor devices can control the dimensions for the active areas and provide less isolation spacing between the active areas, which optimizes manufacturing efficiency and device integration quality.

    摘要翻译： 示例性实施例提供通过反向浅沟槽隔离（STI）结构和其制造方法隔离的三栅极半导体器件。 在示例性工艺中，可以在半导体衬底上形成包括电介质层上的成形层的层叠层。 可以通过蚀刻穿过层叠层而形成一个或多个沟槽。 一个或多个沟槽可以由有源区域材料填充以形成一个或多个有源区域，其可以通过介电层的剩余部分来隔离。 通过去除表层可以暴露活性区域材料的物质。 然后可以在暴露的有源区域材料上形成一个或多个三栅极器件。 示例性三栅极半导体器件可以控制有源区域的尺寸并且在有源区域之间提供更小的隔离间隔，这优化了制造效率和器件集成质量。

    High-K gate dielectric defect gettering using dopants
    24.
    发明授权
    High-K gate dielectric defect gettering using dopants 有权
    使用掺杂剂的高K栅介质缺陷吸杂

    公开(公告)号：US07015088B2

    公开(公告)日：2006-03-21

    申请号：US10335560

    申请日：2002-12-31

    申请人： Luigi Colombo ,  James J. Chambers ,  Antonio Luis Pacheco Rotondaro

    发明人： Luigi Colombo ,  James J. Chambers ,  Antonio Luis Pacheco Rotondaro

    IPC分类号： H01L21/00 ,  H01L21/8242

    CPC分类号： H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6659

    摘要： One or more aspects of the present invention relate to forming a transistor while passivating electrically active defects associated with a top portion of a layer of high-k dielectric material. The layer of high-k dielectric material is utilized to establish a high-k gate dielectric in the transistor. A gate electrode layer is formed over the layer of high-k dielectric material, and is patterned to form a gate structure that includes a gate electrode and the high-k gate dielectric. The electrically active defects are passivated utilizing materials containing dopants that are attracted to and neutralize the defects. The passivated defects thus do not interfere with other transistor doping processes (e.g., forming source and drain regions) and do not adversely affect resulting semiconductor device performance, reliability and yield.

    摘要翻译： 本发明的一个或多个方面涉及形成晶体管，同时钝化与高k电介质材料层的顶部相关联的电活性缺陷。 高k介电材料层用于在晶体管中建立高k栅极电介质。 栅电极层形成在高k电介质材料层上，并被图案化以形成包括栅电极和高k栅电介质的栅结构。 使用含有被吸引并中和缺陷的掺杂剂的材料来钝化电活性缺陷。 钝化的缺陷因此不干扰其它晶体管掺杂过程（例如，形成源极和漏极区），并且不会对所得到的半导体器件性能，可靠性和产量产生不利影响。

    Structure and method to fabricate self-aligned transistors with dual work function metal gate electrodes
    27.
    发明授权
    Structure and method to fabricate self-aligned transistors with dual work function metal gate electrodes 有权
    用双功能金属栅电极制造自对准晶体管的结构和方法

    公开(公告)号：US07005365B2

    公开(公告)日：2006-02-28

    申请号：US10649425

    申请日：2003-08-27

    申请人： James J. Chambers

    发明人： James J. Chambers

    IPC分类号： H01L21/3205 ,  H01L21/4763

    CPC分类号： H01L29/66583 ,  H01L21/28079 ,  H01L21/823842 ,  H01L29/6659 ,  H01L29/7833

    摘要： The present invention provides, in one embodiment, a method (100) of forming dual work function metal gate electrodes in a semiconductor device. The method includes forming a gate dielectric (105) over a substrate (110) and depositing a mold layer (115) having a first opening (120) therein over the gate dielectric (105). The method further includes creating a first metal gate electrode (125) by depositing a first metal in the first opening (120). Other embodiments include an active device (200) produced by the above-described method and method of manufacturing an integrated circuit (300) using the above-described method.

    摘要翻译： 本发明在一个实施例中提供了在半导体器件中形成双功函数金属栅电极的方法（100）。 该方法包括在衬底（110）上形成栅极电介质（105），并且在栅极电介质（105）上沉积其中具有第一开口（120）的模具层（115）。 该方法还包括通过在第一开口（120）中沉积第一金属来产生第一金属栅电极（125）。 其他实施例包括通过上述使用上述方法制造集成电路（300）的方法和方法产生的有源器件（200）。