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    Thermal via arrangement for multi-channel semiconductor device
    21.
    发明授权
    Thermal via arrangement for multi-channel semiconductor device 有权

    公开(公告)号：US10741469B2

    公开(公告)日：2020-08-11

    申请号：US15800611

    申请日：2017-11-01

    Applicant: MEDIATEK INC.

    Inventor： Hsien-Hsin Lin ,  Ming-Tzong Yang ,  Wen-Kai Wan

    IPC: H01L23/367 ,  H01L23/528 ,  H01L23/535 ,  H01L29/78 ,  H01L29/417 ,  H01L27/02

    Abstract: The invention provides a semiconductor device. The semiconductor device includes a gate structure over fin structures arranged in parallel. Each of the fin structures has a drain portion and a source portion on opposite sides of the gate structure. A drain contact structure is positioned over the drain portions of the fin structures. A source contact structure is positioned over the source portions of the fin structures. A first amount of drain via structures is electrically connected to the drain contact structure. A second amount of source via structures is electrically connected to the source contact structure. The sum of the first amount and the second amount is greater than or equal to 2, and the sum of the first amount and the second amount is less than or equal to two times the amount of fin structures.

    Semiconductor package assemblies with system-on-chip (SOC) packages
    22.
    发明授权
    Semiconductor package assemblies with system-on-chip (SOC) packages 有权

    公开(公告)号：US10361173B2

    公开(公告)日：2019-07-23

    申请号：US15365217

    申请日：2016-11-30

    Applicant: MediaTek Inc.

    Inventor： Tzu-Hung Lin ,  Ming-Tzong Yang

    IPC: H01L23/02 ,  H01L23/48 ,  H01L23/52 ,  H01L25/065 ,  H01L25/10 ,  H01L23/31 ,  H01L23/50 ,  H01L23/00 ,  H01L25/18 ,  H05K1/11 ,  H05K1/18

    Abstract: A semiconductor package assembly includes a first semiconductor package. The first semiconductor package has a semiconductor die having pads thereon, first vias disposed on the first semiconductor die, the first vias coupled to the pads. A second semiconductor package is stacked on the first semiconductor package and includes a body having a die-attach surface and a bump-attach surface opposite to the die-attach surface, a first memory die mounted on the bump-attach surface, coupled to the body, and a second memory die mounted on the die-attach surface, coupled to the body through the bonding wires. The number of input/output (I/O) pins of first memory die is different from the number of input/output (I/O) pins of the second memory die.

    Semiconductor package assembly
    23.
    发明授权
    Semiconductor package assembly 有权

    公开(公告)号：US10332830B2

    公开(公告)日：2019-06-25

    申请号：US15592488

    申请日：2017-05-11

    Applicant: MediaTek Inc.

    Inventor： Ming-Tzong Yang ,  Wei-Che Huang ,  Tzu-Hung Lin

    IPC: H01L23/48 ,  H01L23/522 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L25/10 ,  H01L23/498

    Abstract: A semiconductor package assembly having a first semiconductor package, with a first redistribution layer (RDL) structure, a first semiconductor die having through silicon via (TSV) interconnects formed passing therethrough coupled to the first RDL structure, and a second semiconductor package stacked on the first semiconductor package with a second redistribution layer (RDL) structure. The assembly further includes a second semiconductor die without through silicon via (TSV) interconnects formed passing therethrough, coupled to the second RDL structure, and a third semiconductor package stacked on the second semiconductor package, having a third redistribution layer (RDL) structure, a third semiconductor die without through silicon via (TSV) interconnects formed passing therethrough coupled to the third RDL structure. the third semiconductor package is coupled to the second RDL structure by second vias passing through a second molding compound between the third semiconductor package and the second RDL structure.

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