公开(公告)号：US09712130B2

公开(公告)日：2017-07-18

申请号：US14874888

申请日：2015-10-05

Applicant: MediaTek Inc.

Inventor： Ming-Tzong Yang ,  Cheng-Chou Hung ,  Tung-Hsing Lee ,  Wei-Che Huang

IPC: H03H7/01 ,  H03H3/00 ,  H01P1/203 ,  H01P7/08

CPC classification number: H03H7/0115 ,  H01P1/20381 ,  H01P7/082 ,  H03H3/00

Abstract: An implementation of the invention is directed to a passive device cell having a substrate layer, and intermediary layer formed above the substrate layer, and a passive device formed above the intermediary layer. The intermediary layer includes a plurality of LC resonators and a plurality of segmented conductive lines, wherein the plurality of segmented conductive lines are disposed between the plurality of LC resonators.

公开(公告)号：US08836043B2

公开(公告)日：2014-09-16

申请号：US14161570

申请日：2014-01-22

Applicant: Mediatek Inc.

Inventor： Ching-Chung Ko ,  Tung-Hsing Lee

IPC: H01L29/739 ,  H01L21/8249 ,  H01L29/735 ,  H01L29/66 ,  H01L27/06 ,  H01L29/08 ,  H01L29/06

CPC classification number: H01L27/0623 ,  H01L21/8249 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/0821 ,  H01L29/6625 ,  H01L29/735

Abstract: A lateral bipolar junction transistor includes an emitter region; a base region surrounding the emitter region; a gate disposed at least over a portion of the base region; and a collector region surrounding the base region; wherein the portion of the base region under the gate does not under go a threshold voltage implant process.

Abstract translation: 横向双极结晶体管包括发射极区域; 围绕发射极区域的基极区域; 设置在所述基部区域的至少一部分上的栅极; 以及围绕所述基底区域的收集器区域; 其中所述栅极下方的所述基极区域的所述部分未经过阈值电压注入工艺。

公开(公告)号：US20130105899A1

公开(公告)日：2013-05-02

申请号：US13719249

申请日：2012-12-19

Applicant: MEDIATEK INC.

Inventor： Tung-Hsing Lee ,  I-Cheng Lin ,  Wei-Li Tsao

IPC: H01L29/78

CPC classification number: H01L29/78 ,  H01L21/823418 ,  H01L27/0266 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/41775 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66659 ,  H01L29/7835

Abstract: An I/O electrostatic discharge (ESD) device having a gate electrode over a substrate, a gate dielectric layer between the gate electrode and the substrate, a pair of sidewall spacers respectively disposed on two opposite sidewalls of the gate electrode, a first lightly doped drain (LDD) region disposed under one of the sidewall spacers, a source region disposed next to the first LDD region, a second LDD region disposed under the other sidewall spacer, and a drain region disposed next to the second LDD region. The I/O ESD device has an asymmetric LDD configuration. In one embodiment, a junction of the second LDD region is shallower than that of the first LDD region.

Abstract translation: 一种在衬底上具有栅电极的I / O静电放电（ESD）器件，在栅电极和衬底之间的栅极电介质层，分别设置在栅电极的两个相对侧壁上的一对侧壁间隔物，第一轻掺杂 漏极（LDD）区域，设置在第一LDD区域旁边的源极区域，设置在另一侧壁间隔物下方的第二LDD区域和设置在第二LDD区域附近的漏极区域。 I / O ESD器件具有非对称LDD配置。 在一个实施例中，第二LDD区域的结点比第一LDD区域的结浅。

公开(公告)号：US20240019491A1

公开(公告)日：2024-01-18

申请号：US18207122

申请日：2023-06-07

Applicant: MEDIATEK INC.

Inventor： Jia-Horng Shieh ,  Po-Chao Tsao ,  Ming-Cheng Lee ,  Tung-Hsing Lee ,  Chi-Ming Lee ,  Yi-Ju Ting

IPC: G01R31/3185

CPC classification number: G01R31/318511

Abstract: A die-level electrical parameter extraction method includes: obtaining electrical parameters of a plurality of transistor types; obtaining measurement results of a plurality of logic blocks; estimating a mapping relationship between the electrical parameters of the plurality of transistor types and the measurement results of the plurality of logic blocks; and regarding a specific die of a wafer, obtaining die-level measurement of the plurality of logic blocks, and generating die-level electrical parameters of the plurality of transistor types according to the mapping relationship and the die-level measurement results.

公开(公告)号：US09899261B2

公开(公告)日：2018-02-20

申请号：US15365394

申请日：2016-11-30

Applicant: MediaTek Inc.

Inventor： Cheng-Chou Hung ,  Ming-Tzong Yang ,  Tung-Hsing Lee ,  Wei-Che Huang ,  Yu-Hua Huang ,  Tzu-Hung Lin

IPC: H01L23/48 ,  H01L21/768 ,  H01L29/06 ,  H01L21/761 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L21/76898 ,  H01L21/761 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/11 ,  H01L29/0619 ,  H01L29/0623 ,  H01L2224/13 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor package structure having a substrate, wherein the substrate has a front side and a back side, a through silicon via (TSV) interconnect structure formed in the substrate, and a first guard ring doped region and a second guard ring doped region formed in the substrate. The second guard ring doped region is disposed between the first guard ring doped region and the TSV interconnect structure.

公开(公告)号：US09620640B2

公开(公告)日：2017-04-11

申请号：US14450445

申请日：2014-08-04

Applicant: MediaTek Inc.

Inventor： Cheng-Chou Hung ,  Tung-Hsing Lee ,  Bernard Mark Tenbroek ,  Rong-Tang Chen

IPC: H01L21/02 ,  H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/10 ,  H01L29/49 ,  H01L29/786

CPC classification number: H01L29/783 ,  H01L29/0649 ,  H01L29/1095 ,  H01L29/4238 ,  H01L29/4975 ,  H01L29/78615 ,  H01L29/78654 ,  H01L29/78657

Abstract: The invention provides a body-contact metal-oxide-semiconductor field effect transistor (MOSFET) device. The body-contact MOSFET device includes a substrate. An active region is disposed on the substrate. A gate strip is extended along a first direction disposed on a first portion of the active region. A source doped region and a drain doped region are disposed on a second portion and a third portion of the active region, adjacent to opposite sides of the gate strip. The opposite sides of the gate strip are extended along the first direction. A body-contact doped region is disposed on a fourth portion of the active region. The body-contact doped region is separated from the gate strip by a fifth portion of the active region. The fifth portion is not covered by any silicide features.

公开(公告)号：US20250148273A1

公开(公告)日：2025-05-08

申请号：US18926397

申请日：2024-10-25

Applicant: MEDIATEK INC.

Inventor： Khim Jun Koh ,  Chi-Ming Lee ,  Yi-Ju Ting ,  Chung-Kai Chang ,  Po-Chao Tsao ,  Chin-Wei Lin ,  Yu-Lin Yang ,  Tung-Hsing Lee ,  Chin-Tang Lai

IPC: G06N3/0499

Abstract: In an aspect of the disclosure, a method for detecting outlier integrated circuits on a wafer is provided. The method comprises: operating multiple test items for each IC on the wafer to generate measured values of the multiple test items for each IC; selecting a target IC and neighboring ICs on the wafer repeatedly. each time after selecting the target IC executes the following steps: selecting a measured value of the target IC as a target measured value and selecting measured values of the target IC and the neighboring ICs as feature values of the target IC and the neighboring ICs; executing a transformer deep learning model to generate a predicted value of the target measured value; and identifying outlier ICs according to the predicted values of all the target ICs and the corresponding target measured values of all the target ICs.

公开(公告)号：US09640489B2

公开(公告)日：2017-05-02

申请号：US14320725

申请日：2014-07-01

Applicant: MediaTek Inc.

Inventor： Cheng-Chou Hung ,  Tung-Hsing Lee ,  Yu-Hua Huang ,  Ming-Tzong Yang

IPC: H01L21/02 ,  H01L23/00 ,  H01L23/58 ,  H01L29/94 ,  H01L27/08

CPC classification number: H01L23/562 ,  H01L23/564 ,  H01L23/585 ,  H01L27/0805 ,  H01L29/94 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type having a chip region enclosed by a seal ring region. An insulating layer is on the semiconductor substrate. A seal ring structure is embedded in the insulating layer corresponding to the seal ring region. And, a plurality of doping regions are located beneath the first seal ring structure.

公开(公告)号：US09607894B2

公开(公告)日：2017-03-28

申请号：US14621682

申请日：2015-02-13

Applicant: MediaTek Inc.

Inventor： Ming-Tzong Yang ,  Cheng-Chou Hung ,  Tung-Hsing Lee ,  Wei-Che Huang ,  Yu-Hua Huang

IPC: H01L23/66 ,  H01L23/12 ,  H01L25/04 ,  H01L21/768 ,  H01L23/522 ,  H01L31/18 ,  H01L23/48 ,  H01L23/00 ,  H01L21/02 ,  H01L21/268 ,  H01L21/306

CPC classification number: H01L21/76898 ,  H01L21/02107 ,  H01L21/268 ,  H01L21/30625 ,  H01L23/481 ,  H01L23/5227 ,  H01L23/66 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L31/18 ,  H01L2223/6616 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/11 ,  H01L2924/12042 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00

Abstract: An electronic device package has a base and an electronic device chip mounted on the base. The electronic device chip includes a semiconductor substrate having a front side and a back side, a electronic component disposed on the front side of the semiconductor substrate, an interconnect structure disposed on the electronic component, a through hole formed through the semiconductor substrate from the back side of the semiconductor substrate, connecting to the interconnect structure, and a TSV structure disposed in the through hole. The interconnect structure is electrically connected to the RF component, and a thickness of the semiconductor substrate is less than that of the interconnect structure.

公开(公告)号：US20160027772A1

公开(公告)日：2016-01-28

申请号：US14337216

申请日：2014-07-22

Applicant: MEDIATEK INC.

Inventor： Shi-Bai Chen ,  Tung-Hsing Lee

IPC: H01L27/06 ,  H01L49/02

CPC classification number: H01L27/0629 ,  H01L23/5223 ,  H01L28/86 ,  H01L28/87 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated capacitor includes a semiconductor substrate comprising a trench isolation area; a first interlayer dielectric (ILD) layer covering the trench isolation area; a first electrode plate comprising at least a first contact layer in the first ILD layer, wherein the contact layer is disposed directly on the trench isolation area; a second electrode plate in the first ILD layer; and a capacitor dielectric structure between the first electrode plate and the second electrode plate.

Abstract translation: 集成电容器包括：半导体衬底，包括沟槽隔离区域; 覆盖所述沟槽隔离区域的第一层间电介质层（ILD）层; 所述第一电极板包括所述第一ILD层中的至少第一接触层，其中所述接触层直接设置在所述沟槽隔离区域上; 第一ILD层中的第二电极板; 以及在所述第一电极板和所述第二电极板之间的电容器电介质结构。