公开(公告)号：US20160099710A1

公开(公告)日：2016-04-07

申请号：US14968926

申请日：2015-12-15

Applicant: MEDIATEK INC.

Inventor： Yan-Bin Luo ,  Bo-Jiun Chen ,  Ke-Chung Wu

IPC: H03K5/13

CPC classification number: H03K5/131 ,  H03K3/0322 ,  H03K2005/00052 ,  H03K2005/00058

Abstract: A method for performing phase shift control in an electronic device and an associated apparatus are provided, where the method includes: obtaining a set of clock signals corresponding to a set of phases; and controlling a phase shift of an output signal of an oscillator by selectively mixing the set of clock signals into the oscillator according to a set of digital control signals, wherein the phase shift corresponds to the set of digital control signals, and the set of digital control signals carries a set of digital weightings for selectively mixing the set of clock signals. More particularly, the method may include: selectively mixing the set of clock signals into a specific stage of a plurality of stages of the oscillator according to the set of digital control signals.

Abstract translation: 提供一种用于在电子设备和相关设备中进行相移控制的方法，其中所述方法包括：获得与一组相位对应的一组时钟信号; 以及通过根据一组数字控制信号选择性地将所述一组时钟信号混合到所述振荡器中来控制振荡器的输出信号的相移，其中所述相移对应于所述一组数字控制信号，并且所述数字集合 控制信号携带一组数字加权，用于选择性地混合该组时钟信号。 更具体地，该方法可以包括：根据该组数字控制信号，将该组时钟信号选择性地混合到振荡器的多个级的特定级中。

公开(公告)号：US20150091540A1

公开(公告)日：2015-04-02

申请号：US14043859

申请日：2013-10-02

Applicant: MEDIATEK INC.

Inventor： Yan-Bin Luo ,  Chih-Chien Hung

IPC: G05F1/59

CPC classification number: G05F1/59 ,  G05F1/46 ,  G05F1/56

Abstract: A regulator applied to regulate a first reference voltage on an output terminal, the regulator includes: a sensing circuit, arranged to sense a variation of the first reference voltage on the output terminal to generate a sensing signal; and a gain stage, arranged to provide an adjusting current to the output terminal in response to the sensing signal for reducing the variation of the first reference voltage, and the gain stage is coupled in parallel to a loading circuit powered by the first reference voltage.

Abstract translation: 一种调节器，用于调节输出端子上的第一参考电压，所述调节器包括：感测电路，被布置成感测所述输出端上的所述第一参考电压的变化以产生感测信号; 以及增益级，被布置为响应于用于减小第一参考电压的变化的感测信号向输出端提供调节电流，并且增益级与由第一参考电压供电的负载电路并联耦合。

公开(公告)号：US11449453B2

公开(公告)日：2022-09-20

申请号：US17165898

申请日：2021-02-02

Applicant: MEDIATEK INC.

Inventor： Chun-Yuan Yeh ,  Yan-Bin Luo ,  Tse-Hsiang Hsu

IPC: G06F15/78 ,  G06F11/07 ,  G06F13/40 ,  G06F13/20 ,  G06F13/42 ,  H01L25/065

Abstract: A multi-package system includes a first semiconductor package and a second semiconductor package. The first semiconductor package includes a first die and a second die. The second semiconductor package includes a third die. A first processing circuit of the first die communicates with a second processing circuit of the second die through a first configurable input/output (IO) interface circuit of the first die and a third configurable IO interface circuit of the second die that are configured to perform single-ended intra-package communication. The first processing circuit of the first die communicates with a third processing circuit of the third die through a second configurable IO interface circuit of the first die and a fourth configurable IO interface circuit of the third die that are configured to perform differential inter-package communication. The first configurable IO interface circuit and the second configurable IO interface circuit have a same circuit design.

公开(公告)号：US20210326292A1

公开(公告)日：2021-10-21

申请号：US17165898

申请日：2021-02-02

Applicant: MEDIATEK INC.

Inventor： Chun-Yuan Yeh ,  Yan-Bin Luo ,  Tse-Hsiang Hsu

IPC: G06F13/40 ,  G06F13/20 ,  G06F13/42

Abstract: A multi-package system includes a first semiconductor package and a second semiconductor package. The first semiconductor package includes a first die and a second die. The second semiconductor package includes a third die. A first processing circuit of the first die communicates with a second processing circuit of the second die through a first configurable input/output (IO) interface circuit of the first die and a third configurable IO interface circuit of the second die that are configured to perform single-ended intra-package communication. The first processing circuit of the first die communicates with a third processing circuit of the third die through a second configurable IO interface circuit of the first die and a fourth configurable IO interface circuit of the third die that are configured to perform differential inter-package communication. The first configurable IO interface circuit and the second configurable IO interface circuit have a same circuit design.

公开(公告)号：US09590595B2

公开(公告)日：2017-03-07

申请号：US14825149

申请日：2015-08-12

Applicant: MEDIATEK INC.

Inventor： Yan-Bin Luo ,  Chien-Hua Wu ,  Chung-Shi Lin ,  Chih-Hsien Lin

IPC: H03K17/10 ,  H03K3/012 ,  H03K19/0185 ,  H04L25/03 ,  H03K19/0175

CPC classification number: H03K3/012 ,  H03K19/017509 ,  H03K19/018528 ,  H03K19/018585 ,  H04L25/03076

Abstract: A driver circuit for receiving input data and generating an output signal to a termination element is provided, wherein the input data has a first bit and second bit, and the driver circuit includes: a pair of differential output terminals for outputting the output signal, wherein the pair of differential output terminals has a first output terminal and a second output terminal; at least one current mode drive unit, coupled to the pair of differential output terminals, for outputting a current from one of the first output terminal and the second output terminal, and receiving the current from the other of the first output terminal and the second output terminal according to the first bit; and at least one voltage mode drive unit, coupled to the pair of differential output terminals, for providing voltages to the first output terminal and the second output terminal according to the second bit.

Abstract translation: 提供了一种用于接收输入数据并向终端元件产生输出信号的驱动电路，其中输入数据具有第一位和第二位，并且驱动电路包括：一对差分输出端，用于输出输出信号，其中 一对差分输出端子具有第一输出端子和第二输出端子; 耦合到所述一对差分输出端子的至少一个电流模式驱动单元，用于从所述第一输出端子和所述第二输出端子之一输出电流，以及从所述第一输出端子和所述第二输出端子中的另一个接收电流 终端根据第一位; 以及耦合到所述一对差分输出端子的至少一个电压模式驱动单元，用于根据所述第二位向所述第一输出端子和所述第二输出端子提供电压。

公开(公告)号：US09479365B2

公开(公告)日：2016-10-25

申请号：US14737513

申请日：2015-06-12

Applicant: MEDIATEK INC.

Inventor： Tsung-Hsin Chou ,  Chih-Hsien Lin ,  Huai-Te Wang ,  Bo-Jiun Chen ,  Yan-Bin Luo

IPC: H03H7/30 ,  H04L25/03

CPC classification number: H04L25/03057 ,  H04L25/03885 ,  H04L2025/03484 ,  H04L2025/0349 ,  H04L2025/03777 ,  H04L2025/03808

Abstract: A method for performing loop unrolled decision feedback equalization (DFE) and an associated apparatus are provided. The method includes: receiving a tap control signal and an offset control signal from a digital domain of a DFE receiver in an electronic device, and generating DFE information respectively corresponding to the tap control signal and the offset control signal in an analog domain of the DFE receiver; broadcasting the DFE information respectively corresponding to the tap control signal and the offset control signal toward comparators in the DFE receiver; utilizing the comparators to perform comparison operations according to the DFE information respectively corresponding to the tap control signal and the offset control signal to generate comparison results; and selectively adjusting the tap control signal and the offset control signal according to the comparison results, to optimize the DFE information respectively corresponding to the tap control signal and the offset control signal, respectively.

Abstract translation: 提供了一种用于执行循环展开的判决反馈均衡（DFE）和相关联的装置的方法。 该方法包括：从电子设备中的DFE接收机的数字域接收抽头控制信号和偏移控制信号，并且在DFE的模拟域中产生分别对应于抽头控制信号和偏移控制信号的DFE信息 接收器 将分别对应于抽头控制信号和偏移控制信号的DFE信息广播到DFE接收机中的比较器; 利用比较器根据分别对应于抽头控制信号和偏移控制信号的DFE信息执行比较操作，以产生比较结果; 并且根据比较结果选择性地调整抽头控制信号和偏移控制信号，分别优化分别对应于抽头控制信号和偏移控制信号的DFE信息。

公开(公告)号：US20160191037A1

公开(公告)日：2016-06-30

申请号：US14822913

申请日：2015-08-11

Applicant: MEDIATEK INC.

Inventor： Yan-Bin Luo ,  Chien-Hua Wu ,  Chung-Shi Lin ,  Chih-Hsien Lin

IPC: H03K17/10

CPC classification number: H03K17/10 ,  H04L25/0272 ,  H04L25/0282 ,  H04L25/4906

Abstract: A driver circuit for receiving input data and generating an output signal to a termination element is disclosed, wherein the input data has a first bit and second bit, and the driver circuit includes: a pair of differential output terminals, arranged for outputting the output signal, wherein the pair of differential output terminals has a first output terminal and a second output terminal; a current mode drive unit, coupled to the pair of differential output terminals, for outputting a current from one of the first output terminal and the second output terminal, and receiving the current from the other of the first output terminal and the second output terminal according to the first bit; and a voltage mode drive unit, coupled to the pair of differential output terminals, for providing voltages to the first output terminal and the second output terminal according to at least the second bit.

Abstract translation: 公开了一种用于接收输入数据并向终端元件产生输出信号的驱动电路，其中输入数据具有第一位和第二位，并且驱动电路包括：一对差分输出端，用于输出输出信号 ，其中所述一对差分输出端子具有第一输出端子和第二输出端子; 电流模式驱动单元，耦合到所述一对差分输出端子，用于从所述第一输出端子和所述第二输出端子之一输出电流，以及根据所述第一输出端子和所述第二输出端子中的另一个接收所述电流， 到第一位 以及耦合到所述一对差分输出端子的电压模式驱动单元，用于根据至少所述第二位向所述第一输出端子和所述第二输出端子提供电压。

公开(公告)号：US09312846B2

公开(公告)日：2016-04-12

申请号：US14280701

申请日：2014-05-19

Applicant: MEDIATEK INC.

Inventor： Chien-Hua Wu ,  Yan-Bin Luo

IPC: H03B1/00 ,  H03K3/00 ,  H03K17/16 ,  H04L25/00 ,  H04L25/02

CPC classification number: H03K17/16 ,  H03K19/018578 ,  H03K19/018585 ,  H04L25/00 ,  H04L25/0272 ,  H04L25/0282

Abstract: A driver circuit for receiving a data input and generating an output signal according to at least the data input is provided. The driver circuit includes a pair of differential output terminals, a current mode drive unit and a voltage mode drive unit. The pair of differential output terminals has a first output terminal and a second output terminal. The current mode drive unit is arranged for outputting a first reference current from one of the first and second output terminals and receiving the first reference current from the other of the first and the second output terminals according to the first data input. The voltage mode drive unit is arranged for coupling a first reference voltage to one of the first and the second output terminals and coupling a second reference voltage to the other of the first and the second output terminals according to the first data input.

Abstract translation: 提供了用于接收数据输入并至少根据数据输入产生输出信号的驱动电路。 驱动电路包括一对差分输出端子，电流模式驱动单元和电压模式驱动单元。 一对差分输出端子具有第一输出端子和第二输出端子。 电流模式驱动单元布置成从第一和第二输出端之一输出第一参考电流，并根据第一数据输入从第一和第二输出端中的另一个接收第一参考电流。 电压模式驱动单元用于将第一参考电压耦合到第一和第二输出端之一，并根据第一数据输入将第二参考电压耦合到第一和第二输出端中的另一个。

公开(公告)号：US20160056980A1

公开(公告)日：2016-02-25

申请号：US14740264

申请日：2015-06-16

Applicant: MEDIATEK INC.

Inventor： Huai-Te Wang ,  Tsung-Hsin Chou ,  Chih-Hsien Lin ,  Bo-Jiun Chen ,  Yan-Bin Luo

IPC: H04L25/03 ,  H03L7/099 ,  H03L7/087 ,  H03L7/091 ,  H03L7/095

CPC classification number: H04L25/03057 ,  H03L7/087 ,  H03L7/091 ,  H03L7/095 ,  H03L7/099 ,  H04L7/0025 ,  H04L7/0331

Abstract: A method for performing data sampling control in an electronic device and an associated apparatus are provided, where the method includes the steps of: detecting whether a data pattern of a received signal of a decision feedback equalizer (DFE) receiver in the electronic device matches a predetermined data pattern, to selectively trigger a data sampling time shift configuration of the DFE receiver; and when the data sampling time shift configuration is triggered, utilizing a phase shift clock, rather than a normal clock corresponding to a normal configuration of the DFE receiver, as an edge sampler clock of an edge sampler in the DFE receiver, to lock onto edge timing of the received signal, and controlling the phase shift clock and the normal clock to have different phases, respectively, to shift data sampling time of the DFE receiver, for performing data sampling in the DFE receiver.

Abstract translation: 提供了一种在电子设备和相关设备中执行数据采样控制的方法，其中该方法包括以下步骤：检测电子设备中的判决反馈均衡器（DFE）接收机的接收信号的数据模式是否匹配 预定数据模式，以选择性地触发DFE接收机的数据采样时移配置; 并且当触发数据采样时移配置时，利用相移时钟而不是与DFE接收机的正常配置对应的正常时钟作为DFE接收机中的边缘采样器的边缘采样器时钟来锁定到边缘 接收信号的定时，并且分别控制相移时钟和正常时钟以具有不同的相位，以移位DFE接收机的数据采样时间，以便在DFE接收机中执行数据采样。

公开(公告)号：US20150349763A1

公开(公告)日：2015-12-03

申请号：US14294130

申请日：2014-06-02

Applicant: MEDIATEK INC.

Inventor： Yan-Bin Luo ,  Bo-Jiun Chen ,  Ke-Chung Wu

IPC: H03K5/13

CPC classification number: H03K5/131 ,  H03K3/0322 ,  H03K2005/00052 ,  H03K2005/00058

Abstract: A method for performing phase shift control in an electronic device and an associated apparatus are provided, where the method includes: obtaining a set of clock signals corresponding to a set of phases, wherein any two phases of the set of phases are different from each other; and controlling a phase shift of an output signal of an oscillator by selectively mixing the set of clock signals into the oscillator according to a set of digital weighting control signals, wherein the phase shift corresponds to the set of digital weighting control signals, and the set of digital weighting control signals carries a set of digital weightings for selectively mixing the set of clock signals. More particularly, the method may include: selectively mixing the set of clock signals into a specific stage of a plurality of stages of the oscillator according to the set of digital weighting control signals.

Abstract translation: 提供了一种用于在电子设备和相关设备中执行相移控制的方法，其中该方法包括：获得与一组相位相对应的一组时钟信号，其中该组相位中的任何两个相位彼此不同 ; 以及通过根据一组数字加权控制信号选择性地将所述一组时钟信号混合到所述振荡器中来控制振荡器的输出信号的相移，其中所述相移对应于所述一组数字加权控制信号，并且所述组 数字加权控制信号携带一组数字加权，用于选择性地混合该组时钟信号。 更具体地说，该方法可以包括：根据该组数字加权控制信号，将该组时钟信号选择性地混合到振荡器的多个级的特定级中。