公开(公告)号：US20170250165A1

公开(公告)日：2017-08-31

申请号：US15592488

申请日：2017-05-11

Applicant: MediaTek Inc.

Inventor： Ming-Tzong YANG ,  Wei-Che HUANG ,  Tzu-Hung LIN

IPC: H01L25/10 ,  H01L23/538 ,  H01L23/00

CPC classification number: H01L23/5226 ,  H01L23/3171 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/25 ,  H01L25/105 ,  H01L2224/12105 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/24137 ,  H01L2224/24146 ,  H01L2224/24226 ,  H01L2224/25171 ,  H01L2224/73209 ,  H01L2224/73253 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1436 ,  H01L2924/18161 ,  H01L2924/18162

Abstract: A semiconductor package assembly having a first semiconductor package, with a first redistribution layer (RDL) structure, a first semiconductor die having through silicon via (TSV) interconnects formed passing therethrough coupled to the first RDL structure, and a second semiconductor package stacked on the first semiconductor package with a second redistribution layer (RDL) structure. The assembly further includes a second semiconductor die without through silicon via (TSV) interconnects formed passing therethrough, coupled to the second RDL structure, and a third semiconductor package stacked on the second semiconductor package, having a third redistribution layer (RDL) structure, a third semiconductor die without through silicon via (TSV) interconnects formed passing therethrough coupled to the third RDL structure. the third semiconductor package is coupled to the second RDL structure by second vias passing through a second molding compound between the third semiconductor package and the second RDL structure.

公开(公告)号：US20170141041A1

公开(公告)日：2017-05-18

申请号：US15338652

申请日：2016-10-31

Applicant: MEDIATEK INC.

Inventor： Tzu-Hung LIN ,  Nai-Wei LIU ,  I-Hsuan PENG ,  Wei-Che HUANG

IPC: H01L23/538 ,  H01L25/065 ,  H01L25/10 ,  H01L23/31

Abstract: The invention provides a semiconductor package assembly. The semiconductor package assembly includes a redistribution layer (RDL) structure having a first surface and a second surface opposite to the first substrate. The RDL structure includes a redistribution layer (RDL) contact pad arranged close to the second surface. A passivation layer is disposed on the RDL contact pad. The passivation layer has an opening corresponding to the RDL contact pad such that the RDL contact pad is exposed to the opening. A first distance between a first position of the opening and a central point of the opening is different from a second distance between a second position of the opening and the central point of the opening in a plan view.

公开(公告)号：US20170084525A1

公开(公告)日：2017-03-23

申请号：US15365394

申请日：2016-11-30

Applicant: MediaTek Inc.

Inventor： Cheng-Chou HUNG ,  Ming-Tzong YANG ,  Tung-Hsing LEE ,  Wei-Che HUANG ,  Yu-Hua HUANG ,  Tzu-Hung LIN

IPC: H01L23/498 ,  H01L21/768 ,  H01L29/06 ,  H01L21/761

CPC classification number: H01L21/76898 ,  H01L21/761 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/11 ,  H01L29/0619 ,  H01L29/0623 ,  H01L2224/13 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor package structure having a substrate, wherein the substrate has a front side and a back side, a through silicon via (TSV) interconnect structure formed in the substrate, and a first guard ring doped region and a second guard ring doped region formed in the substrate. The second guard ring doped region is disposed between the first guard ring doped region and the TSV interconnect structure.

公开(公告)号：US20170040266A1

公开(公告)日：2017-02-09

申请号：US15331016

申请日：2016-10-21

Applicant: MEDIATEK INC.

Inventor： Tzu-Hung LIN ,  I-Hsuan PENG ,  Nai-Wei LIU ,  Wei-Che HUANG ,  Che-Ya CHOU

IPC: H01L23/66 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538

CPC classification number: H01L23/66 ,  H01L23/49816 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/19 ,  H01L24/20 ,  H01L25/105 ,  H01L25/16 ,  H01L2223/6677 ,  H01L2224/02379 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/1421 ,  H01L2924/1435 ,  H01L2924/1438 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/3025

Abstract: The invention provides a semiconductor package assembly. The semiconductor package assembly includes a first semiconductor package including a first redistribution layer (RDL) structure having a first surface and a second surface opposite to the first substrate. The first RDL structure includes a plurality of first conductive traces close to the first surface of the first RDL structure. An antenna pattern is disposed close to the second surface of the first RDL structure. A first semiconductor die is disposed on the first surface of the first RDL structure and electrically coupled to the first RDL structure. A plurality of conductive structures is disposed on the first surface of the first RDL structure and electrically coupled to the first RDL structure. The plurality of conductive structures is spaced apart from the antenna pattern through the plurality of first conductive traces of the first RDL structure.

Abstract translation: 本发明提供一种半导体封装组件。 半导体封装组件包括第一半导体封装，其包括具有第一表面和与第一基板相对的第二表面的第一再分布层（RDL）结构。 第一RDL结构包括靠近第一RDL结构的第一表面的多个第一导电迹线。 天线图案靠近第一RDL结构的第二表面设置。 第一半导体管芯设置在第一RDL结构的第一表面上并电耦合到第一RDL结构。 多个导电结构设置在第一RDL结构的第一表面上并电耦合到第一RDL结构。 多个导电结构通过第一RDL结构的多个第一导电迹线与天线图案间隔开。

公开(公告)号：US20130270670A1

公开(公告)日：2013-10-17

申请号：US13855873

申请日：2013-04-03

Applicant: MEDIATEK INC.

Inventor： Ming-Tzong YANG ,  Yu-Hua HUANG ,  Wei-Che HUANG

IPC: H01L23/538

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L23/528 ,  H01L23/5384 ,  H01L24/11 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/42356 ,  H01L2224/02372 ,  H01L2224/0912 ,  H01L2225/06541

Abstract: The invention provides a semiconductor package with a through silicon via (TSV) interconnect. An exemplary embodiment of the semiconductor package with a TSV interconnect includes a semiconductor substrate, having a front side and a back side. A contact array is disposed on the front side of the semiconductor substrate. An isolation structure is disposed in the semiconductor substrate, underlying the contact array. The TSV interconnect is formed through the semiconductor substrate, overlapping with the contact array and the isolation structure.

Abstract translation: 本发明提供一种具有通硅通孔（TSV）互连的半导体封装。 具有TSV互连的半导体封装的示例性实施例包括具有前侧和后侧的半导体衬底。 接触阵列设置在半导体衬底的前侧。 隔离结构设置在半导体衬底中，位于接触阵列的下面。 TSV互连通过半导体衬底形成，与接触阵列和隔离结构重叠。