公开(公告)号：US20170084583A1

公开(公告)日：2017-03-23

申请号：US15365217

申请日：2016-11-30

Applicant: MediaTek Inc.

Inventor： Tzu-Hung LIN ,  Ming-Tzong YANG

IPC: H01L25/065 ,  H01L25/10

CPC classification number: H01L25/0657 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/50 ,  H01L24/17 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/10 ,  H01L25/105 ,  H01L25/18 ,  H01L2224/0237 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73209 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2225/06572 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/18162 ,  H05K1/112 ,  H05K1/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package assembly includes a first semiconductor package. The first semiconductor package has a semiconductor die having pads thereon, first vias disposed on the first semiconductor die, the first vias coupled to the pads. A second semiconductor package is stacked on the first semiconductor package and includes a body having a die-attach surface and a bump-attach surface opposite to the die-attach surface, a first memory die mounted on the bump-attach surface, coupled to the body, and a second memory die mounted on the die-attach surface, coupled to the body through the bonding wires. The number of input/output (I/O) pins of first memory die is different from the number of input/output (I/O) pins of the second memory die.

公开(公告)号：US20170250165A1

公开(公告)日：2017-08-31

申请号：US15592488

申请日：2017-05-11

Applicant: MediaTek Inc.

Inventor： Ming-Tzong YANG ,  Wei-Che HUANG ,  Tzu-Hung LIN

IPC: H01L25/10 ,  H01L23/538 ,  H01L23/00

CPC classification number: H01L23/5226 ,  H01L23/3171 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/25 ,  H01L25/105 ,  H01L2224/12105 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/24137 ,  H01L2224/24146 ,  H01L2224/24226 ,  H01L2224/25171 ,  H01L2224/73209 ,  H01L2224/73253 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1436 ,  H01L2924/18161 ,  H01L2924/18162

Abstract: A semiconductor package assembly having a first semiconductor package, with a first redistribution layer (RDL) structure, a first semiconductor die having through silicon via (TSV) interconnects formed passing therethrough coupled to the first RDL structure, and a second semiconductor package stacked on the first semiconductor package with a second redistribution layer (RDL) structure. The assembly further includes a second semiconductor die without through silicon via (TSV) interconnects formed passing therethrough, coupled to the second RDL structure, and a third semiconductor package stacked on the second semiconductor package, having a third redistribution layer (RDL) structure, a third semiconductor die without through silicon via (TSV) interconnects formed passing therethrough coupled to the third RDL structure. the third semiconductor package is coupled to the second RDL structure by second vias passing through a second molding compound between the third semiconductor package and the second RDL structure.

公开(公告)号：US20170084525A1

公开(公告)日：2017-03-23

申请号：US15365394

申请日：2016-11-30

Applicant: MediaTek Inc.

Inventor： Cheng-Chou HUNG ,  Ming-Tzong YANG ,  Tung-Hsing LEE ,  Wei-Che HUANG ,  Yu-Hua HUANG ,  Tzu-Hung LIN

IPC: H01L23/498 ,  H01L21/768 ,  H01L29/06 ,  H01L21/761

CPC classification number: H01L21/76898 ,  H01L21/761 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/11 ,  H01L29/0619 ,  H01L29/0623 ,  H01L2224/13 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor package structure having a substrate, wherein the substrate has a front side and a back side, a through silicon via (TSV) interconnect structure formed in the substrate, and a first guard ring doped region and a second guard ring doped region formed in the substrate. The second guard ring doped region is disposed between the first guard ring doped region and the TSV interconnect structure.

公开(公告)号：US20130270670A1

公开(公告)日：2013-10-17

申请号：US13855873

申请日：2013-04-03

Applicant: MEDIATEK INC.

Inventor： Ming-Tzong YANG ,  Yu-Hua HUANG ,  Wei-Che HUANG

IPC: H01L23/538

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L23/528 ,  H01L23/5384 ,  H01L24/11 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/42356 ,  H01L2224/02372 ,  H01L2224/0912 ,  H01L2225/06541

Abstract: The invention provides a semiconductor package with a through silicon via (TSV) interconnect. An exemplary embodiment of the semiconductor package with a TSV interconnect includes a semiconductor substrate, having a front side and a back side. A contact array is disposed on the front side of the semiconductor substrate. An isolation structure is disposed in the semiconductor substrate, underlying the contact array. The TSV interconnect is formed through the semiconductor substrate, overlapping with the contact array and the isolation structure.

Abstract translation: 本发明提供一种具有通硅通孔（TSV）互连的半导体封装。 具有TSV互连的半导体封装的示例性实施例包括具有前侧和后侧的半导体衬底。 接触阵列设置在半导体衬底的前侧。 隔离结构设置在半导体衬底中，位于接触阵列的下面。 TSV互连通过半导体衬底形成，与接触阵列和隔离结构重叠。

公开(公告)号：US20180138104A1

公开(公告)日：2018-05-17

申请号：US15800611

申请日：2017-11-01

Applicant: MEDIATEK INC.

Inventor： Hsien-Hsin LIN ,  Ming-Tzong YANG ,  Wen-Kai WAN

IPC: H01L23/367 ,  H01L29/78 ,  H01L23/535 ,  H01L23/528

Abstract: The invention provides a semiconductor device. The semiconductor device includes a gate structure over fin structures arranged in parallel. Each of the fin structures has a drain portion and a source portion on opposite sides of the gate structure. A drain contact structure is positioned over the drain portions of the fin structures. A source contact structure is positioned over the source portions of the fin structures. A first amount of drain via structures is electrically connected to the drain contact structure. A second amount of source via structures is electrically connected to the source contact structure. The sum of the first amount and the second amount is greater than or equal to 2, and the sum of the first amount and the second amount is less than or equal to two times the amount of fin structures.

公开(公告)号：US20170110406A1

公开(公告)日：2017-04-20

申请号：US15393387

申请日：2016-12-29

Applicant: MediaTek Inc.

Inventor： Ming-Tzong YANG ,  Cheng-Chou HUNG ,  Wei-Che HUANG ,  Yu-Hua HUANG ,  Tzu-Hung LIN ,  Kuei-Ti CHAN ,  Ruey-Beei WU ,  Kai-Bin WU

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/498 ,  H01L23/00 ,  H01L21/768 ,  H01L23/48

CPC classification number: H01L23/5384 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/5386 ,  H01L24/14 ,  H01L25/0657 ,  H01L2224/16146 ,  H01L2225/06541 ,  H01L2225/06544

Abstract: The invention provides a semiconductor package assembly with a TSV interconnect. The semiconductor package assembly includes a first semiconductor package mounted on a base, having: a semiconductor die, a semiconductor substrate, and a first array of TSV interconnects and a second array of TSV interconnects formed through the semiconductor substrate, wherein the first array and second array of TSV interconnects are separated by an interval region. The assembly further includes a second semiconductor die mounted on the first semiconductor package, having a ground pad thereon. One of the TSV interconnects of the first semiconductor package has a first terminal coupled to the ground pad of the second semiconductor die and a second terminal coupled to an interconnection structure disposed on a front side of the semiconductor substrate.

公开(公告)号：US20170084488A1

公开(公告)日：2017-03-23

申请号：US15365435

申请日：2016-11-30

Applicant: MediaTek Inc.

Inventor： Cheng-Chou HUNG ,  Ming-Tzong YANG ,  Tung-Hsing LEE ,  Wei-Che HUANG ,  Yu-Hua HUANG ,  Tzu-Hung LIN

IPC: H01L21/768 ,  H01L23/00 ,  H01L29/06 ,  H01L23/48 ,  H01L21/761

CPC classification number: H01L21/76898 ,  H01L21/761 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/11 ,  H01L29/0619 ,  H01L29/0623 ,  H01L2224/13 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming a semiconductor package structure is provided. The method for forming a semiconductor package structure includes providing a substrate, wherein the substrate has a front side and a back side, forming a first guard ring doped region and a second guard ring doped region in the substrate, wherein the first guard ring doped region and the second guard ring doped region have different conductive types, forming a trench through the substrate from a back side of the substrate, conformally forming an insulating layer lining the back side of the substrate, a bottom surface and sidewalls of the trench, removing a portion of the insulating layer on the back side of the substrate to form a through via, and forming a conductive material in the through via, wherein a through silicon via (TSV) interconnect structure is formed by the insulating layer and the conductive material.

公开(公告)号：US20160079220A1

公开(公告)日：2016-03-17

申请号：US14741796

申请日：2015-06-17

Applicant: MediaTek Inc.

Inventor： Tzu-Hung LIN ,  Ming-Tzong YANG

IPC: H01L25/18 ,  H01L25/065 ,  H01L23/48 ,  H05K1/18 ,  H01L23/00 ,  H01L23/50 ,  H01L23/31 ,  H05K1/11

CPC classification number: H01L25/0657 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/50 ,  H01L24/17 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/10 ,  H01L25/105 ,  H01L25/18 ,  H01L2224/0237 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73209 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2225/06572 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/18162 ,  H05K1/112 ,  H05K1/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The invention provides a semiconductor package assembly. The semiconductor package assembly includes a first semiconductor package. The first semiconductor package includes a first semiconductor die having first pads thereon. First vias are disposed on the first semiconductor die, coupled to the first pads. A first dynamic random access memory (DRAM) die is mounted on the first semiconductor die, coupled to the first vias. A second semiconductor package is stacked on the first semiconductor package. The second semiconductor package includes a body having a die-attach surface and a bump-attach surface opposite to the die-attach surface. A second dynamic random access memory (DRAM) die is mounted on the die-attach surface, coupled to the body through the bonding wires. The number of input/output (I/O) pins of first DRAM die is different from the number of input/output (I/O) pins of the second DRAM die.

Abstract translation: 本发明提供一种半导体封装组件。 半导体封装组件包括第一半导体封装。 第一半导体封装包括其上具有第一焊盘的第一半导体管芯。 第一通孔设置在第一半导体管芯上，耦合到第一焊盘。 第一动态随机存取存储器（DRAM）管芯安装在第一半导体管芯上，耦合到第一通孔。 第二半导体封装堆叠在第一半导体封装上。 第二半导体封装包括具有管芯附接表面和与管芯附接表面相对的凸起附着表面的主体。 第二动态随机存取存储器（DRAM）裸片安装在芯片附接表面上，通过接合线耦合到主体。 第一DRAM裸片的输入/输出（I / O）引脚的数量与第二DRAM裸片的输入/输出（I / O）引脚的数量不同。

公开(公告)号：US20140070346A1

公开(公告)日：2014-03-13

申请号：US13790060

申请日：2013-03-08

Applicant: MEDIATEK INC.

Inventor： Ming-Tzong YANG ,  Cheng-Chou HUNG ,  Tung-Hsing LEE ,  Wei-Che HUANG ,  Yu-Hua HUANG

IPC: H01L23/522 ,  H01L31/18

CPC classification number: H01L21/76898 ,  H01L21/02107 ,  H01L21/268 ,  H01L21/30625 ,  H01L23/481 ,  H01L23/5227 ,  H01L23/66 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L31/18 ,  H01L2223/6616 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/11 ,  H01L2924/12042 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00

Abstract: The invention provides a radio-frequency (RF) device package and a method for fabricating the same. An exemplary embodiment of a radio-frequency (RF) device package includes a base, wherein a radio-frequency (RF) device chip is mounted on the base. The RF device chip includes a semiconductor substrate having a front side and a back side. A radio-frequency (RF) component is disposed on the front side of the semiconductor substrate. An interconnect structure is disposed on the RF component, wherein the interconnect structure is electrically connected to the RF component, and a thickness of the semiconductor substrate is less than that of the interconnect structure. A through hole is formed through the semiconductor substrate from the back side of the semiconductor substrate, and is connected to the interconnect structure. A TSV structure is disposed in the through hole.

Abstract translation: 本发明提供一种射频（RF）器件封装及其制造方法。 射频（RF）器件封装的示例性实施例包括基座，其中射频（RF）器件芯片安装在基座上。 RF器件芯片包括具有前侧和后侧的半导体衬底。 射频（RF）部件设置在半导体衬底的前侧。 互连结构设置在RF部件上，其中互连结构电连接到RF部件，并且半导体衬底的厚度小于互连结构的厚度。 从半导体衬底的背面穿过半导体衬底形成一个通孔，并连接到互连结构。 TSV结构设置在通孔中。

公开(公告)号：US20230154824A1

公开(公告)日：2023-05-18

申请号：US18155322

申请日：2023-01-17

Applicant: Chee-Wee LIU ,  MEDIATEK INC.

Inventor： Ming-Tzong YANG ,  Hsien-Hsin LIN ,  Wen-Kai WAN ,  Chia-Che CHUNG ,  Chee-Wee LIU

IPC: H01L23/373 ,  H01L21/768 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L23/373 ,  H01L21/768 ,  H01L29/785 ,  H01L29/66795 ,  H01L2029/7858

Abstract: A semiconductor device and method for forming same. According to an embodiment. The method provides a base substrate, forms a heat dissipation substrate on the base substrate, wherein a thermal conductivity of the heat dissipation substrate is between 200 Wm−1K−1and 1200 Wm−1K−1. This method further forms a device layer on the heat dissipation substrate, wherein the device layer comprises a transistor. The method further removes the base substrate.