公开(公告)号：US20140254731A1

公开(公告)日：2014-09-11

申请号：US14197812

申请日：2014-03-05

Applicant: Microchip Technology Incorporated

Inventor： Stephen Bowling ,  Samar Naik ,  Igor Wojewoda

IPC: H04L7/00

CPC classification number: H04L7/0079 ,  H04L7/0331 ,  H04L7/044 ,  H04L25/49 ,  H04L25/4902

Abstract: A system for determining a unit time of a serial transmission protocol, wherein the serial transmission protocol defines a unit time (UT) by transmitting a calibration pulse having a predetermined length of N*UT and wherein a receiver is operated by system clock, includes: a clock divider for dividing the system clock by M, wherein M evenly divides N, and a detector for sampling a received data nibble length by using a dithered sampling clock.

Abstract translation: 一种用于确定串行传输协议的单位时间的系统，其中所述串行传输协议通过发送具有预定长度的N * UT的校准脉冲来定义单位时间（UT），并且其中接收机由系统时钟操作，包括： 用于将系统时钟除以M的时钟分频器，其中M均匀地划分N，以及用于使用抖动采样时钟对接收数据半字节长度进行采样的检测器。

公开(公告)号：US10860408B2

公开(公告)日：2020-12-08

申请号：US15970159

申请日：2018-05-03

Applicant: Microchip Technology Incorporated

Inventor： Stephen Bowling ,  Igor Wojewoda ,  Manivannan Balu

IPC: G06F11/00 ,  G06F11/07 ,  G06F13/40

Abstract: A semiconductor die includes a feedback path coupled to the output pin, and an integrity monitor circuit (IMC). The output pin is communicatively coupled to the logic. The IMC is configured to receive a data value. The IMC is further configured to receive measured data value from the output pin routed through the feedback path, compare the data value and the measured data value, and, based on the comparison, determine whether an error has occurred.

公开(公告)号：US10795783B2

公开(公告)日：2020-10-06

申请号：US16158471

申请日：2018-10-12

Applicant: Microchip Technology Incorporated

Inventor： Igor Wojewoda ,  Bryan Kris ,  Stephen Bowling ,  Yong Yuenyongsgool

IPC: G06F11/00 ,  G06F11/16 ,  G06F11/14 ,  H03K5/19

Abstract: A clock monitor includes a test clock input, as a reference clock input, another clock input, a measurement circuit, and control logic. The measurement circuit generates a measurement of a frequency or a duty cycle of the test clock input using the reference clock input, which is compared to a threshold. The control logic determines whether the measurement exceeded the threshold and, based on the measurement exceeding the threshold, cause generation of another measurement of a frequency or a duty cycle using the third clock input in combination with the first clock input or the reference clock input. The control logic may determine whether the other measurement exceeded a threshold and, based on such a determination, further determine that the test clock input or the reference clock input are faulty.

公开(公告)号：US10352998B2

公开(公告)日：2019-07-16

申请号：US15785792

申请日：2017-10-17

Applicant: Microchip Technology Incorporated

Inventor： Stephen Bowling ,  Igor Wojewoda ,  Dereck Fernandes ,  Manivannan Balu ,  Yong Yuenyongsgool ,  Timothy Phoenix ,  Steve Bradley

IPC: G01R31/317 ,  G01R31/3177 ,  G06F15/80 ,  G11C29/14 ,  G11C29/26 ,  G11C29/48 ,  G11C29/04

Abstract: In an embedded device with a plurality of processor cores, each core has a static random access memory (SRAM), a memory built-in self-test (MBIST) controller associated with the SRAM, an MBIST access port coupled with the MBIST controller, an MBIST finite state machine (FSM) coupled with the MBIST access port via a first multiplexer, and a JTAG interface coupled with the MBIST access ports of each processor core via the multiplexer of each processor core.

公开(公告)号：US20190114235A1

公开(公告)日：2019-04-18

申请号：US16158471

申请日：2018-10-12

Applicant: Microchip Technology Incorporated

Inventor： Igor Wojewoda ,  Bryan Kris ,  Stephen Bowling ,  Yong Yuenyongsgool

IPC: G06F11/16 ,  G06F11/34 ,  G06F11/14

Abstract: A clock monitor includes a test clock input, as a reference clock input, another clock input, a measurement circuit, and control logic. The measurement circuit generates a measurement of a frequency or a duty cycle of the test clock input using the reference clock input, which is compared to a threshold. The control logic determines whether the measurement exceeded the threshold and, based on the measurement exceeding the threshold, cause generation of another measurement of a frequency or a duty cycle using the third clock input in combination with the first clock input or the reference clock input. The control logic may determine whether the other measurement exceeded a threshold and, based on such a determination, further determine that the test clock input or the reference clock input are faulty.

公开(公告)号：US09858083B2

公开(公告)日：2018-01-02

申请号：US14204208

申请日：2014-03-11

Applicant: Microchip Technology Incorporated

Inventor： Michael I. Catherwood ,  Brant Ivey ,  Igor Wojewoda ,  David Mickey ,  Joseph Kanellopoulos

IPC: G06F9/44 ,  G06F9/445

CPC classification number: G06F9/4401 ,  G06F8/656 ,  G06F9/441

Abstract: A central processing unit with dual boot capabilities is disclosed comprising an instruction memory further comprising a first and second memory area which are configured to be individually programmable, wherein first and second memory area can be assigned to an active memory from which instructions are executed and an inactive memory, respectively. The instruction set for the central processing unit comprises a dedicated instruction that allows to perform a swap from the an active memory area to an inactive memory area, wherein the swap is performed by executing the dedicated instruction in the active memory followed by a program flow change instruction in the active memory, whereupon the inactive memory becomes the new active memory and the active memory becomes the new inactive memory and execution of instructions continues in the new active memory.

公开(公告)号：US09590649B2

公开(公告)日：2017-03-07

申请号：US14883842

申请日：2015-10-15

Applicant: Microchip Technology Incorporated

Inventor： James E. Bartling ,  Igor Wojewoda ,  Kevin Kilzer

IPC: H03M1/12 ,  H03K17/96 ,  G06F1/32 ,  H03M1/00 ,  H03M1/50

CPC classification number: H03M1/12 ,  G06F1/32 ,  H03K17/9622 ,  H03K2217/960725 ,  H03M1/00 ,  H03M1/1225 ,  H03M1/1245 ,  H03M1/50

Abstract: A micro-coded sequencer controls complex conversion sequences independent of a central processing unit (CPU). Micro-coding provides for easily adding new process steps and/or updating existing process steps. Such a programmable sequencer in combination with an analog-to-digital conversion module such as an analog-to-digital converter (ADC) or a charge time measurement unit (CTMU), and digital processing circuits may be configured to work independently of the CPU in combination with the micro-coded sequencer. Thereby providing self-sufficient operation in low power modes when the CPU and other high power modules are in a low power sleep mode. Such a peripheral can execute data collection and processing thereof, then wake the CPU only when needed, thereby saving power. Furthermore, this peripheral does not require CPU processing so that time critical applications that do require control by the CPU can operate more efficiently and with less operating overhead burden.

Abstract translation: 微编码序列器控制独立于中央处理单元（CPU）的复杂转换序列。 微编码提供了轻松添加新的流程步骤和/或更新现有的流程步骤。 与诸如模数转换器（ADC）或充电时间测量单元（CTMU）之类的模数转换模块和数字处理电路组合的这种可编程序排序器可被配置为独立于CPU 与微编码序列器结合使用。 因此，当CPU和其他高功率模块处于低功耗睡眠模式时，能够以低功耗模式提供自给自足的操作。 这样的外设可以执行数据收集和处理，然后在需要时唤醒CPU，从而节省电力。 此外，该外设不需要CPU处理，因此需要CPU控制的时间关键应用程序可以更有效地运行，同时减少运营负担。