公开(公告)号：US10387048B2

公开(公告)日：2019-08-20

申请号：US16006192

申请日：2018-06-12

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Eric Lee ,  Qiang Tang ,  Ali Feiz Zarrin Ghalam ,  Hoon Choi ,  Daesik Song

IPC: G11C16/32 ,  G06F3/06 ,  G11C16/26 ,  G06F12/0802 ,  G11C7/10 ,  G11C7/22 ,  G06F12/02

Abstract: Memory device including a controller configured to cause the memory device to generate a first clock edge of a first clock signal in response to a first clock edge of a second clock signal, to generate a second, opposite, clock edge of the first clock signal immediately following the first clock edge of the first clock signal in response to a second, opposite, clock edge of the second clock signal immediately following the first clock edge of the second clock signal, and to latch data for output from the memory device in response to the second clock edge of the first clock signal.

公开(公告)号：US20220374370A1

公开(公告)日：2022-11-24

申请号：US17880226

申请日：2022-08-03

Applicant: Micron Technology, Inc.

Inventor： Guan Wang ,  Ali Feiz Zarrin Ghalam ,  Chin-Yu Chen ,  Jongin Kim

IPC: G06F13/16 ,  H03K3/017 ,  G11C16/32

Abstract: An electrical circuit device includes a signal bus comprising a plurality of parallel signal paths and a calibration circuit, operatively coupled with the signal bus. The calibration circuit can perform operations including determining a representative duty cycle for a plurality of signals transferred via the plurality of parallel signal paths, the plurality of signals comprising a plurality of duty cycles and comparing the representative duty cycle for the plurality of signals transferred via the plurality of parallel signal paths to a reference value to determine a comparison result. The calibration circuit can perform further operations including adjusting, based on the comparison result, a trim value associated with the plurality of duty cycles of the plurality of signals to compensate for distortion in the plurality of duty cycles and calibrating the plurality of duty cycles of the plurality of signals using the adjusted trim value.

公开(公告)号：US20210218388A1

公开(公告)日：2021-07-15

申请号：US17214262

申请日：2021-03-26

Applicant: Micron Technology, Inc.

Inventor： Guan Wang ,  Qiang Tang ,  Ali Feiz Zarrin Ghalam

IPC: H03K3/017 ,  G06F1/04 ,  G06F1/10 ,  G11C7/22 ,  H04L25/06 ,  G11C29/02 ,  H03K5/156 ,  H04L7/00 ,  H04L25/02

Abstract: Several embodiments of electrical circuit devices and systems with clock distortion calibration circuitry are disclosed herein. In one embodiment, an electrical circuit device includes an electrical circuit die having clock distortion calibration circuitry to calibrate a clock signal. The clock distortion calibration circuitry is configured to compare a first duty cycle of a first voltage signal of the clock signal to a second duty cycle of a second voltage signal of the clock signal. Based on the comparison, the clock distortion calibration circuitry is configured to adjust a trim value associated with at least one of the first and the second duty cycles of the first and the second voltage signals, respectively, to calibrate at least one of the first and the second duty cycles and account for duty cycle distortion encountered as the clock signal propagates through a clock tree of the electrical circuit device.

公开(公告)号：US20210057007A1

公开(公告)日：2021-02-25

申请号：US17092046

申请日：2020-11-06

Applicant: Micron Technology, Inc.

Inventor： Agatino Massimo Maccarrone ,  Luigi Pilolli ,  Ali Feiz Zarrin Ghalam ,  Chin Yu Chen

IPC: G11C7/22 ,  G11C7/10

Abstract: Disclosed are systems and methods involving memory-side write training to improve data valid window. In one implementation, a method for performing memory-side write training may comprise delaying a rising edge or a falling edge of a first data signal, delaying a rising edge or a falling edge of a second data signal, and aligning the two adjusted signals to reduce a window of time that the data signals are not valid and thereby improve or optimize the data valid window (DVW) of a memory array. According to implementations herein, various edges of data signals and clock signals may be adjusted or delayed via dedicated trim cells or circuitry present in the data paths located on the memory side of a system.

公开(公告)号：US10861517B1

公开(公告)日：2020-12-08

申请号：US16447727

申请日：2019-06-20

Applicant: Micron Technology, Inc.

Inventor： Agatino Massimo Maccarrone ,  Luigi Pilolli ,  Ali Feiz Zarrin Ghalam ,  Chin Yu Chen

IPC: G11C7/10 ,  G11C7/22

Abstract: Disclosed are systems and methods involving memory-side write training to improve data valid window. In one implementation, a method for performing memory-side write training may comprise delaying a rising edge or a falling edge of a first data signal, delaying a rising edge or a falling edge of a second data signal, and aligning the two adjusted signals to reduce a window of time that the data signals are not valid and thereby improve or optimize the data valid window (DVW) of a memory array. According to implementations herein, various edges of data signals and clock signals may be adjusted or delayed via dedicated trim cells or circuitry present in the data paths located on the memory side of a system.

公开(公告)号：US10727816B2

公开(公告)日：2020-07-28

申请号：US16204841

申请日：2018-11-29

Applicant: Micron Technology, Inc.

Inventor： Guan Wang ,  Qiang Tang ,  Ali Feiz Zarrin Ghalam

IPC: G06F1/10 ,  H03K3/017 ,  H04L25/06 ,  H03K5/156 ,  G11C7/22 ,  G11C29/02 ,  H04L7/00 ,  H04L25/02 ,  G06F1/04

Abstract: Several embodiments of electrical circuit devices and systems with clock distortion calibration circuitry are disclosed herein. In one embodiment, an electrical circuit device includes an electrical circuit die having clock distortion calibration circuitry to calibrate a clock signal. The clock distortion calibration circuitry is configured to compare a first duty cycle of a first voltage signal of the clock signal to a second duty cycle of a second voltage signal of the clock signal. Based on the comparison, the clock calibration circuitry is configured to adjust a trim value associated with at least one of the first and the second duty cycles of the first and the second voltage signals, respectively, to calibrate at least one of the first and the second duty cycles and account for duty cycle distortion encountered as the clock signal propagates through a clock tree of the electrical circuit device.

公开(公告)号：US20190355400A1

公开(公告)日：2019-11-21

申请号：US16531244

申请日：2019-08-05

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kaveh Shakeri ,  Ali Feiz Zarrin Ghalam

IPC: G11C7/22 ,  G11C8/18 ,  G11C7/10 ,  G11C16/04 ,  G11C8/06

Abstract: A wave pipeline includes a plurality of data paths, a clock signal path, and a return clock signal path. Each data path includes an input node, an output node, and a data stage between the input node and the output node. Each data path has a different delay between the input node and the output node. A first data path of the plurality of data paths has a first delay and each of the other data paths of the plurality of data paths have a delay less than the first delay. The clock signal path provides a clock signal to the data stage of each data path. The return clock signal path provides a return clock signal from the data stage of the first data path. The return clock signal triggers data out of the data stage of each data path of the plurality of data paths.

公开(公告)号：US10360956B2

公开(公告)日：2019-07-23

申请号：US15834279

申请日：2017-12-07

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kaveh Shakeri ,  Ali Feiz Zarrin Ghalam ,  Qiang Tang ,  Eric N. Lee

IPC: G11C7/10 ,  G11C7/22 ,  G11C7/06 ,  G11C8/06 ,  G11C8/04 ,  G11C8/18 ,  G11C16/04

Abstract: A wave pipeline includes a first stage, a plurality of second stages, and a third stage. The first stage receives a data signal representative of data and a clock signal, and may process the data at a first data rate equal to a clock rate of the clock signal. Each second stage may process respective data in response to a respective clock cycle received from the first stage at a second data rate equal to the first data rate times the number of second stages. The third stage may process data received from each second stage at the first data rate. The first stage divides the data signal and the clock signal between the plurality of second stages. The third stage merges the respective data and the respective clock cycles from each of the plurality of second stages to provide a merged data signal and a return clock signal.

公开(公告)号：US20190180801A1

公开(公告)日：2019-06-13

申请号：US15834279

申请日：2017-12-07

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kaveh Shakeri ,  Ali Feiz Zarrin Ghalam ,  Qiang Tang ,  Eric N. Lee

IPC: G11C7/22 ,  G11C7/06 ,  G11C8/06 ,  G11C8/18 ,  G11C8/04 ,  G11C7/10

CPC classification number: G11C7/222 ,  G11C7/06 ,  G11C7/1006 ,  G11C7/1039 ,  G11C7/1057 ,  G11C7/106 ,  G11C8/04 ,  G11C8/06 ,  G11C8/18 ,  G11C16/0483

Abstract: A wave pipeline includes a first stage, a plurality of second stages, and a third stage. The first stage receives a data signal representative of data and a clock signal, and may process the data at a first data rate equal to a clock rate of the clock signal. Each second stage may process respective data in response to a respective clock cycle received from the first stage at a second data rate equal to the first data rate times the number of second stages. The third stage may process data received from each second stage at the first data rate. The first stage divides the data signal and the clock signal between the plurality of second stages. The third stage merges the respective data and the respective clock cycles from each of the plurality of second stages to provide a merged data signal and a return clock signal.

公开(公告)号：US20140258619A1

公开(公告)日：2014-09-11

申请号：US13793347

申请日：2013-03-11

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Dean K. Nobunaga ,  Ali Feiz Zarrin Ghalam ,  Xiaojiang Guo ,  Eric N. Lee

IPC: G06F12/08

CPC classification number: G06F3/0629 ,  G06F3/0604 ,  G06F3/061 ,  G06F3/0683 ,  G06F12/0802 ,  G06F12/0893 ,  G06F13/1684 ,  G06F13/4068 ,  G06F2212/1016 ,  G06F2212/3042 ,  G11C5/066 ,  G11C7/1048 ,  G11C8/12 ,  G11C11/00

Abstract: Apparatuses and methods for reducing capacitance on a data bus are disclosed herein. In accordance with one or more described embodiments, an apparatus may comprise a plurality of memories coupled to an internal data bus and a command and address bus, each of the memories configured to receive a command on the command and address bus. One of the plurality of memories may be coupled to an external data bus. The one of the plurality of memories may be configured to provide program data to the internal data bus when the command comprises a program command and another of the plurality of memories is a target memory of the program command and may be configured to provide read data to the external data bus when the command comprises a read command and the another of the plurality of memories is a target memory of the read command.

Abstract translation: 本文公开了用于减小数据总线上的电容的装置和方法。 根据一个或多个所描述的实施例，装置可以包括耦合到内部数据总线和命令和地址总线的多个存储器，每个存储器被配置为在命令和地址总线上接收命令。 多个存储器中的一个可以耦合到外部数据总线。 多个存储器中的一个可以被配置为当命令包括程序命令时向内部数据总线提供程序数据，并且多个存储器中的另一个是程序命令的目标存储器，并且可以被配置为将读取数据提供给 当命令包括读取命令并且多个存储器中的另一个是读取命令的目标存储器时的外部数据总线。