-
公开(公告)号：US20180366166A1
公开(公告)日：2018-12-20
申请号：US16110294
申请日：2018-08-23
Applicant: Micron Technology, Inc.
Inventor： Dean K. Nobunaga , June Lee , Chih Liang Chen
CPC classification number: G11C7/1072 , G06F13/1694 , G11C7/10 , G11C7/1045 , G11C7/22 , G11C14/0009 , G11C16/10 , Y02D10/14
Abstract: The present disclosure includes methods, and circuits, for operating a memory device. One method embodiment for operating a memory device includes controlling data transfer through a memory interface in an asynchronous mode by writing data to the memory device at least partially in response to a write enable signal on a first interface contact, and reading data from the memory device at least partially in response to a read enable signal on a second interface contact. The method further includes controlling data transfer in a synchronous mode by transferring data at least partially in response to a clock signal on the first interface contact, and providing a bidirectional data strobe signal on an interface contact not utilized in the asynchronous mode.
-
2.发明授权Apparatuses and methods for a memory die architecture including an interface memory 有权包括接口存储器的存储器管芯结构的装置和方法公开(公告)号：US09190133B2
公开(公告)日：2015-11-17
申请号：US13793347
申请日：2013-03-11
Applicant: Micron Technology, Inc.
Inventor： Dean K. Nobunaga , Ali Feiz Zarrin Ghalam , Xiaojiang Guo , Eric N. Lee
CPC classification number: G06F3/0629 , G06F3/0604 , G06F3/061 , G06F3/0683 , G06F12/0802 , G06F12/0893 , G06F13/1684 , G06F13/4068 , G06F2212/1016 , G06F2212/3042 , G11C5/066 , G11C7/1048 , G11C8/12 , G11C11/00
Abstract: Apparatuses and methods for reducing capacitance on a data bus are disclosed herein. In accordance with one or more described embodiments, an apparatus may comprise a plurality of memories coupled to an internal data bus and a command and address bus, each of the memories configured to receive a command on the command and address bus. One of the plurality of memories may be coupled to an external data bus. The one of the plurality of memories may be configured to provide program data to the internal data bus when the command comprises a program command and another of the plurality of memories is a target memory of the program command and may be configured to provide read data to the external data bus when the command comprises a read command and the another of the plurality of memories is a target memory of the read command.
Abstract translation: 本文公开了用于减小数据总线上的电容的装置和方法。 根据一个或多个所描述的实施例，装置可以包括耦合到内部数据总线和命令和地址总线的多个存储器，每个存储器被配置为在命令和地址总线上接收命令。 多个存储器中的一个可以耦合到外部数据总线。 多个存储器中的一个可以被配置为当命令包括程序命令时向内部数据总线提供程序数据，并且多个存储器中的另一个是程序命令的目标存储器，并且可以被配置为将读取数据提供给 当命令包括读取命令并且多个存储器中的另一个是读取命令的目标存储器时的外部数据总线。
-
公开(公告)号：US09159373B2
公开(公告)日：2015-10-13
申请号：US13938039
申请日：2013-07-09
Applicant: Micron Technology, Inc.
Inventor： Dean K. Nobunaga
CPC classification number: G11C5/025 , G06F12/0246 , G06F2212/7203 , G11C16/0483 , G11C16/105 , G11C19/00
Abstract: Methods and apparatuses for an enhanced block copy. One embodiment is reading data from a source block located in a first portion of the memory device, and programming the data to a target block located in a second portion of the memory device. The first and second portions are communicatively coupled by data lines extending across the portions. The data lines are communicatively uncoupled between the first and second portions for at least one of the reading and programming acts.
Abstract translation: 用于增强块拷贝的方法和装置。 一个实施例是从位于存储器件的第一部分中的源块读取数据，并将数据编程到位于存储器件的第二部分中的目标块。 第一和第二部分通过跨越部分延伸的数据线通信地耦合。 对于读取和编程动作中的至少一个，数据线在第一和第二部分之间通信地分离。
-
公开(公告)号：US20140153335A1
公开(公告)日：2014-06-05
申请号：US14063773
申请日：2013-10-25
Applicant: Micron Technology, Inc.
Inventor： Dean K. Nobunaga , June Lee , Chih Liang Chen
IPC: G11C16/10
CPC classification number: G11C7/1072 , G06F13/1694 , G11C7/10 , G11C7/1045 , G11C7/22 , G11C14/0009 , G11C16/10 , Y02D10/14
Abstract: The present disclosure includes methods, and circuits, for operating a memory device. One method embodiment for operating a memory device includes controlling data transfer through a memory interface in an asynchronous mode by writing data to the memory device at least partially in response to a write enable signal on a first interface contact, and reading data from the memory device at least partially in response to a read enable signal on a second interface contact. The method further includes controlling data transfer in a synchronous mode by transferring data at least partially in response to a clock signal on the first interface contact, and providing a bidirectional data strobe signal on an interface contact not utilized in the asynchronous mode.
Abstract translation: 本公开包括用于操作存储器件的方法和电路。 用于操作存储器件的一个方法实施例包括通过至少部分地响应于第一接口触点上的写入使能信号向存储器件写入数据来控制通过异步模式的存储器接口的数据传输，以及从存储器件读取数据 至少部分地响应于第二接口触点上的读使能信号。 该方法还包括通过至少部分地响应于第一接口触点上的时钟信号传送数据，并且在不在异步模式下使用的接口触点上提供双向数据选通信号，来以同步模式控制数据传输。
-
公开(公告)号：US10083725B2
公开(公告)日：2018-09-25
申请号：US15674586
申请日：2017-08-11
Applicant: Micron Technology, Inc.
Inventor： Dean K. Nobunaga , June Lee , Chih Liang Chen
CPC classification number: G11C7/1072 , G06F13/1694 , G11C7/10 , G11C7/1045 , G11C7/22 , G11C14/0009 , G11C16/10 , Y02D10/14
Abstract: The present disclosure includes methods, and circuits, for operating a memory device. One method embodiment for operating a memory device includes controlling data transfer through a memory interface in an asynchronous mode by writing data to the memory device at least partially in response to a write enable signal on a first interface contact, and reading data from the memory device at least partially in response to a read enable signal on a second interface contact. The method further includes controlling data transfer in a synchronous mode by transferring data at least partially in response to a clock signal on the first interface contact, and providing a bidirectional data strobe signal on an interface contact not utilized in the asynchronous mode.
-
Patent Agency Ranking
公开(公告)号：US09710182B2
公开(公告)日：2017-07-18
申请号：US14942701
申请日：2015-11-16
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Dean K. Nobunaga , Ali Feiz Zarrin Ghalam , Xiaojiang Guo , Eric N. Lee
IPC: G06F12/00 , G11C11/00 , G06F3/06 , G06F12/0893 , G11C8/12 , G11C5/06 , G11C7/10 , G06F12/0802 , G06F13/40 , G06F13/16
CPC classification number: G06F3/0629 , G06F3/0604 , G06F3/061 , G06F3/0683 , G06F12/0802 , G06F12/0893 , G06F13/1684 , G06F13/4068 , G06F2212/1016 , G06F2212/3042 , G11C5/066 , G11C7/1048 , G11C8/12 , G11C11/00
Abstract: Apparatuses and methods for reducing capacitance on a data bus are disclosed herein. In accordance with one or more described embodiments, an apparatus may comprise a plurality of memories coupled to an internal data bus and a command and address bus, each of the memories configured to receive a command on the command and address bus. One of the plurality of memories may be coupled to an external data bus. The one of the plurality of memories may be configured to provide program data to the internal data bus when the command comprises a program command and another of the plurality of memories is a target memory of the program command and may be configured to provide read data to the external data bus when the command comprises a read command and the another of the plurality of memories is a target memory of the read command.
-
7.发明申请APPARATUSES AND METHODS FOR A MEMORY DIE ARCHITECTURE INCLUDING AN INTERFACE MEMORY 有权包含界面记忆的记忆体建筑的装置和方法公开(公告)号：US20160070504A1
公开(公告)日：2016-03-10
申请号：US14942701
申请日：2015-11-16
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Dean K. Nobunaga , Ali Feiz Zarrin Ghalam , Xiaojiang Guo , Eric N. Lee
CPC classification number: G06F3/0629 , G06F3/0604 , G06F3/061 , G06F3/0683 , G06F12/0802 , G06F12/0893 , G06F13/1684 , G06F13/4068 , G06F2212/1016 , G06F2212/3042 , G11C5/066 , G11C7/1048 , G11C8/12 , G11C11/00
Abstract: Apparatuses and methods for reducing capacitance on a data bus are disclosed herein. In accordance with one or more described embodiments, an apparatus may comprise a plurality of memories coupled to an internal data bus and a command and address bus, each of the memories configured to receive a command on the command and address bus. One of the plurality of memories may be coupled to an external data bus, The one of the plurality of memories may be configured to provide program data to the internal data bus when the command comprises a program command and another of the plurality of memories is a target memory of the program command and may be configured to provide read data to the external data bus when the command comprises a read command and the another of the plurality of memories is a target memory of the read command.
Abstract translation: 本文公开了用于减小数据总线上的电容的装置和方法。 根据一个或多个所描述的实施例，装置可以包括耦合到内部数据总线和命令和地址总线的多个存储器，每个存储器被配置为在命令和地址总线上接收命令。 多个存储器中的一个可以耦合到外部数据总线。多个存储器中的一个存储器可以被配置为当命令包括程序命令时将程序数据提供给内部数据总线，并且多个存储器中的另一个是 目标存储器，并且可以被配置为当命令包括读取命令并且多个存储器中的另一个是读取命令的目标存储器时，向外部数据总线提供读取数据。
-
公开(公告)号：US20200126601A1
公开(公告)日：2020-04-23
申请号：US16663958
申请日：2019-10-25
Applicant: Micron Technology, Inc.
Inventor： Dean K. Nobunaga , June Lee , Chih Liang Chen
Abstract: The present disclosure includes methods, and circuits, for operating a memory device. One method embodiment for operating a memory device includes controlling data transfer through a memory interface in an asynchronous mode by writing data to the memory device at least partially in response to a write enable signal on a first interface contact, and reading data from the memory device at least partially in response to a read enable signal on a second interface contact. The method further includes controlling data transfer in a synchronous mode by transferring data at least partially in response to a clock signal on the first interface contact, and providing a bidirectional data strobe signal on an interface contact not utilized in the asynchronous mode.
-
公开(公告)号：US20170345468A1
公开(公告)日：2017-11-30
申请号：US15674586
申请日：2017-08-11
Applicant: Micron Technology, Inc.
Inventor： Dean K. Nobunaga , June Lee , Chih Liang Chen
CPC classification number: G11C7/1072 , G06F13/1694 , G11C7/10 , G11C7/1045 , G11C7/22 , G11C14/0009 , G11C16/10 , Y02D10/14
Abstract: The present disclosure includes methods, and circuits, for operating a memory device. One method embodiment for operating a memory device includes controlling data transfer through a memory interface in an asynchronous mode by writing data to the memory device at least partially in response to a write enable signal on a first interface contact, and reading data from the memory device at least partially in response to a read enable signal on a second interface contact. The method further includes controlling data transfer in a synchronous mode by transferring data at least partially in response to a clock signal on the first interface contact, and providing a bidirectional data strobe signal on an interface contact not utilized in the asynchronous mode.
-
公开(公告)号：US20160064048A1
公开(公告)日：2016-03-03
申请号：US14938193
申请日：2015-11-11
Applicant: Micron Technology, Inc.
Inventor： Dean K. Nobunaga , June Lee , Chih Liang Chen
CPC classification number: G11C7/1072 , G06F13/1694 , G11C7/10 , G11C7/1045 , G11C7/22 , G11C14/0009 , G11C16/10 , Y02D10/14
Abstract: The present disclosure includes methods, and circuits, for operating a memory device. One method embodiment for operating a memory device includes controlling data transfer through a memory interface in an asynchronous mode by writing data to the memory device at least partially in response to a write enable signal on a first interface contact, and reading data from the memory device at least partially in response to a read enable signal on a second interface contact. The method further includes controlling data transfer in a synchronous mode by transferring data at least partially in response to a clock signal on the first interface contact, and providing a bidirectional data strobe signal on an interface contact not utilized in the asynchronous mode.
-
-
-
-
-
-
-
-
-
Search Results
16
records
(took 0.015 seconds)
