公开(公告)号：US20220076770A1

公开(公告)日：2022-03-10

申请号：US17013089

申请日：2020-09-04

Applicant: Micron Technology, Inc.

Inventor： Hongmei Wang ,  Nevil N. Gajera ,  Mingdong Cui ,  Fabio Pellizzer

IPC: G11C29/38

Abstract: An example apparatus can include a memory array and control circuitry. The memory array can include a first portion including a first plurality of memory cells. The memory array can further include a second portion including a second plurality of memory cells. The control circuitry can be configured to designate the first portion as active responsive to a determination that the first portion passed a performance test. The control circuitry can be configured to designate the second portion as inactive responsive to a determination that the second portion failed the performance test.

公开(公告)号：US11271153B2

公开(公告)日：2022-03-08

申请号：US16904385

申请日：2020-06-17

Applicant: Micron Technology, Inc.

Inventor： Lorenzo Fratin ,  Fabio Pellizzer

IPC: H01L45/00 ,  H01L27/24 ,  G11C13/00

Abstract: A self-selecting memory cell may be composed of a memory material that changes threshold voltages based on the polarity of the voltage applied across it. Such a memory cell may be formed at the intersection of a conductive pillar and electrode plane in a memory array. A dielectric material may be formed between the memory material of the memory cell and the corresponding electrode plane. The dielectric material may form a barrier that prevents harmful interactions between the memory material and the material that makes up the electrode plane. In some cases, the dielectric material may also be positioned between the memory material and the conductive pillar to form a second dielectric barrier. The second dielectric barrier may increase the symmetry of the memory array or prevent harmful interactions between the memory material and an electrode cylinder or between the memory material and the conductive pillar.

公开(公告)号：US20220013170A1

公开(公告)日：2022-01-13

申请号：US17486134

申请日：2021-09-27

Applicant: Micron Technology, Inc.

Inventor： Fabio Pellizzer

IPC: G11C13/00

Abstract: The present disclosure includes apparatuses, methods, and systems for sensing two memory cells to determine one data value. An embodiment includes a memory having a plurality of memory cells and circuitry configured to sense memory states of each of two memory cells to determine one data value. One data value is determined by sensing the memory state of a first one of the two memory cells using a first sensing voltage in a sense window between a first threshold voltage distribution corresponding to a first memory state and a second threshold voltage distribution corresponding to a second memory state and sensing the memory state of a second one of the two memory cells using a second sensing voltage in the sense window. The first and second sensing voltages are selectably closer in the sense window to the first threshold voltage distribution or the second threshold voltage distribution.

公开(公告)号：US11152065B2

公开(公告)日：2021-10-19

申请号：US16863175

申请日：2020-04-30

Applicant: Micron Technology, Inc.

Inventor： Innocenzo Tortorelli ,  Andrea Redaelli ,  Agostino Pirovano ,  Fabio Pellizzer ,  Mario Allegra ,  Paolo Fantini

IPC: G11C13/02 ,  G11C13/00 ,  G11C11/56 ,  H01L27/24 ,  H01L45/00

Abstract: Methods, systems, and devices related to techniques to access a self-selecting memory device are described. A self-selecting memory cell may store one or more bits of data represented by different threshold voltages of the self-selecting memory cell. A programming pulse may be varied to establish the different threshold voltages by modifying one or more time durations during which a fixed level of voltage or current is maintained across the self-selecting memory cell. The self-selecting memory cell may include a chalcogenide alloy. A non-uniform distribution of an element in the chalcogenide alloy may determine a particular threshold voltage of the self-selecting memory cell. The shape of the programming pulse may be configured to modify a distribution of the element in the chalcogenide alloy based on a desired logic state of the self-selecting memory cell.

公开(公告)号：US20210233584A1

公开(公告)日：2021-07-29

申请号：US17165555

申请日：2021-02-02

Applicant: Micron Technology, Inc.

Inventor： Karthik Sarpatwari ,  Fabio Pellizzer ,  Jessica Chen ,  Nevil Gajera

IPC: G11C13/00

Abstract: Methods, systems, and devices for dirty write on power off are described. In an example, the described techniques may include writing memory cells of a device according to one or more parameters (e.g., reset current amplitude), where each memory cell is associated with a storage element storing a value based on a material property associated with the storage element. Additionally, the described techniques may include identifying, after writing the memory cells, an indication of power down for the device and refreshing, before the power down of the device, a portion of the memory cells based on identifying the indication of the power down for the device. In some cases, refreshing includes modifying at least one of the one or more parameters for a write operation for the portion of the memory cells.

公开(公告)号：US11049769B2

公开(公告)日：2021-06-29

申请号：US16111004

申请日：2018-08-23

Applicant: Micron Technology, Inc.

Inventor： Fabio Pellizzer ,  Antonino Rigano ,  Roberto Somaschini

IPC: H01L21/768 ,  H01L45/00 ,  H01L27/24 ,  H01L23/522 ,  H01L21/033 ,  H01L21/311

Abstract: Methods and structures provide horizontal conductive lines of fine pitch and self-aligned contacts extending from them, where the contacts have at least one dimension with a more relaxed pitch. Buried hard mask materials permit self-alignment of the lines and contacts without a critical mask, such as for word-line electrode lines and word-line contacts in a memory device.

公开(公告)号：US11018300B2

公开(公告)日：2021-05-25

申请号：US16665955

申请日：2019-10-28

Applicant: Micron Technology, Inc.

Inventor： Agostino Pirovano ,  Fabio Pellizzer ,  Anna Maria Conti ,  Andrea Redaelli ,  Innocenzo Tortorelli

IPC: H01L45/00 ,  H01L27/24

Abstract: A multi-layer memory device with an array having multiple memory decks of self-selecting memory cells is provided in which N memory decks may be fabricated with N+1 mask operations. The multiple memory decks may be self-aligned and certain manufacturing operations may be performed for multiple memory decks at the same time. For example, patterning a bit line direction of a first memory deck and a word line direction in a second memory deck above the first memory deck may be performed in a single masking operation, and both decks may be etched in a same subsequent etching operation. Such techniques may provide efficient fabrication which may allow for enhanced throughput, additional capacity, and higher yield for fabrication facilities relative to processing techniques in which each memory deck is processed using two or more mask and etch operations per memory deck.

公开(公告)号：US10937829B2

公开(公告)日：2021-03-02

申请号：US16550532

申请日：2019-08-26

Applicant: Micron Technology, Inc.

Inventor： Agostino Pirovano ,  Andrea Redaelli ,  Fabio Pellizzer ,  Innocenzo Tortorelli

IPC: H01L27/24 ,  H01L45/00 ,  H01L27/115

Abstract: In an example, a memory array may include a plurality of first dielectric materials and a plurality of stacks, where each respective first dielectric material and each respective stack alternate, and where each respective stack comprises a first conductive material and a storage material. A second conductive material may pass through the plurality of first dielectric materials and the plurality of stacks. Each respective stack may further include a second dielectric material between the first conductive material and the second conductive material.

公开(公告)号：US10854674B2

公开(公告)日：2020-12-01

申请号：US15693102

申请日：2017-08-31

Applicant: Micron Technology, Inc.

Inventor： Marcello Ravasio ,  Samuele Sciarrillo ,  Fabio Pellizzer ,  Innocenzo Tortorelli ,  Roberto Somaschini ,  Cristina Casellato ,  Riccardo Mottadelli

IPC: H01L27/24 ,  H01L45/00

Abstract: The disclosed technology relates generally to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. In one aspect, a method of fabricating cross-point memory arrays comprises forming a memory cell material stack which includes a first active material and a second active material over the first active material, wherein one of the first and second active materials comprises a storage material and the other of the first and second active materials comprises a selector material. The method of fabricating cross-point arrays further comprises patterning the memory cell material stack, which includes etching through at least one of the first and second active materials of the memory cell material stack, forming protective liners on sidewalls of the at least one of the first and second active materials after etching through the one of the first and second active materials, and further etching the memory cell material stack after forming the protective liners on the sidewalls of the one of the first and second active materials.

公开(公告)号：US20200303462A1

公开(公告)日：2020-09-24

申请号：US16892459

申请日：2020-06-04

Applicant: Micron Technology, Inc.

Inventor： Fabio Pellizzer ,  Andrea Redaelli ,  Agostino Pirovano ,  Innocenzo Tortorelli

IPC: H01L27/24 ,  H01L45/00 ,  H01L49/02

Abstract: The present disclosure includes memory cells having resistors, and methods of forming the same. An example method includes forming a first conductive line, forming a second conductive line, and forming a memory element between the first conductive line and the second conductive line. Forming the memory element can include forming one or more memory materials, and forming a resistor in series with the one or more memory materials. The resistor can be configured to reduce a capacitive discharge through the memory element during a state transition of the memory element.