公开(公告)号：US10777562B1

公开(公告)日：2020-09-15

申请号：US16353343

申请日：2019-03-14

Applicant: Micron Technology, Inc.

Inventor： Gurtej S. Sandhu ,  John A. Smythe

IPC: H01L27/24 ,  H01L27/108

Abstract: A method used in forming integrated circuitry comprises forming a plurality of conductive vias comprising conductive material. The conductive vias are spaced relative one another by intermediate material. A discontinuous material is formed atop the conductive material of the vias and atop the intermediate material that is between the vias. Metal material is formed atop, directly against, and between the discontinuous material and atop and directly against the conductive material of the vias. The metal material is of different composition from that of the discontinuous material and is above the intermediate material that is between the vias. The metal material with discontinuous material there-below is formed to comprise a conductive line that is atop the intermediate material that is between the vias and is directly against individual of the vias. Structures independent of method are disclosed.

公开(公告)号：US10766057B2

公开(公告)日：2020-09-08

申请号：US15856373

申请日：2017-12-28

Applicant: Micron Technology, Inc.

Inventor： Ken Tokashiki ,  Gurtej S. Sandhu

IPC: B08B9/00 ,  B08B7/00 ,  H01L21/67 ,  H01L21/683

Abstract: A method of cleaning a tool for forming a semiconductor device includes heating a wafer comprising a ceramic material to heat at least the ceramic material, positioning the heated wafer on an electrostatic chuck of a tool for forming a semiconductor device such that deposits located proximate the heated wafer are heated to vaporize at least some of the deposits, and removing the vaporized deposits from the tool. Related methods of forming semiconductor devices, related systems, and related cleaning wafers are disclosed.

公开(公告)号：US10748594B2

公开(公告)日：2020-08-18

申请号：US15895671

申请日：2018-02-13

Applicant: Micron Technology, Inc.

Inventor： Gurtej S. Sandhu ,  Wayne I. Kinney

IPC: G11C11/16 ,  G11C16/32 ,  G11C11/14

Abstract: Methods, systems, and devices for enabling fast pulse operation are described. A threshold voltage of a selection component and a requisite duration for a voltage applied to a selection component to reach a threshold voltage in response to a voltage generated by an external source may be determined. The threshold voltage may correspond to a voltage at which the selection component is configured to release electric charge. A voltage may then be generated and applied to an access line that is in electronic communication with the selection component and a memory cell for at least the requisite duration. Electric charge may be stored at the selection component during the requisite duration and transferred to memory cell after the requisite duration.

公开(公告)号：US20200251339A1

公开(公告)日：2020-08-06

申请号：US16834766

申请日：2020-03-30

Applicant: Micron Technology, Inc.

Inventor： Gurtej S. Sandhu

IPC: H01L21/033 ,  H01L21/768 ,  B81C1/00 ,  H01L21/308

Abstract: A method of forming a structure comprises forming a pattern of self-assembled nucleic acids over a material. The pattern of self-assembled nucleic acids is exposed to at least one repair enzyme to repair defects in the pattern. The repaired pattern of self-assembled nucleic acids is transferred to the material to form features therein. A method of decreasing defect density in self-assembled nucleic acids is also disclosed. Self-assembled nucleic acids exhibiting an initial defect density are formed over at least a portion of a material and the self-assembled nucleic acids are exposed to at least one repair enzyme to repair defects in the self-assembled nucleic acids. Additional methods are also disclosed.

公开(公告)号：US20200227428A1

公开(公告)日：2020-07-16

申请号：US16248248

申请日：2019-01-15

Applicant: Micron Technology, Inc.

Inventor： Haitao Liu ,  Kamal M. Karda ,  Gurtej S. Sandhu ,  Sanh D. Tang ,  Akira Goda ,  Lifang Xu

IPC: H01L27/11573 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  G11C16/08 ,  H01L21/28 ,  H01L23/532

Abstract: A memory can have a stacked memory array that can have a plurality of levels of memory cells. Each respective level of memory cells can be commonly coupled to a respective access line. A plurality of drivers can be above the stacked memory array. Each respective driver can have a monocrystalline semiconductor with a conductive region coupled to a respective access line.

公开(公告)号：US10680036B2

公开(公告)日：2020-06-09

申请号：US16451938

申请日：2019-06-25

Applicant: Micron Technology, Inc.

Inventor： Gurtej S. Sandhu ,  Sumeet C. Pandey

IPC: H01L27/22 ,  H01L43/08 ,  H01L43/02 ,  H01L43/10 ,  H01L43/12

Abstract: A magnetic cell includes magnetic, secondary oxide, and getter seed regions. During formation, a diffusive species is transferred from a precursor magnetic material to the getter seed region, due to a chemical affinity elicited by a getter species. The depletion of the magnetic material enables crystallization of the depleted magnetic material through crystal structure propagation from a neighboring crystalline material, without interference from the now-enriched getter seed region. This promotes high tunnel magnetoresistance and high magnetic anisotropy strength. Also during formation, another diffusive species is transferred from a precursor oxide material to the getter seed region, due to a chemical affinity elicited by another getter species. The depletion of the oxide material enables lower electrical resistance and low damping in the cell structure. Methods of fabrication and semiconductor devices are also disclosed.

公开(公告)号：US10665593B2

公开(公告)日：2020-05-26

申请号：US16421286

申请日：2019-05-23

Applicant: Micron Technology, Inc.

Inventor： Gurtej S. Sandhu ,  Kamal M. Karda

IPC: H01L27/108

Abstract: Some embodiments include a memory cell having a transistor with a channel region between a first source/drain region and a second source/drain region. A controlled-conductivity region is adjacent the first source/drain region. The controlled-conductivity region has a low-conductivity mode and a high-conductivity mode. The high-conductivity mode has a conductivity at least 106 greater than a conductivity of the low-conductivity mode. The channel region includes a first material having a first bandgap, and the controlled-conductivity region includes a second material having a second bandgap which is greater than the first bandgap. A charge-storage device is electrically coupled to the first source/drain region through the controlled-conductivity region. A bitline is electrically coupled to the second source/drain region.

公开(公告)号：US20200066637A1

公开(公告)日：2020-02-27

申请号：US16112333

申请日：2018-08-24

Applicant: Micron Technology, Inc.

Inventor： Sumeet C. Pandey ,  Gurtej S. Sandhu

IPC: H01L23/535 ,  H01L27/108 ,  H01L29/08 ,  H01L23/532

Abstract: Some embodiments include an integrated assembly which has a semiconductor material with a surface. A first layer is over and directly against the surface. The first layer includes oxygen and a first metal. The relative amount of oxygen to the first metal is less than or equal to an amount sufficient to form stoichiometric metal oxide throughout the first layer. A second metal is over and directly against the first layer. A second layer is over and directly against the second metal. The second layer includes nitrogen and a third metal. Some embodiments include an integrated assembly which has a semiconductor material with a surface. A metal is adjacent the surface and is spaced from the surface by a distance of less than or equal to about 10 Å. There is no metal germanide or metal silicide between the metal and the surface.

公开(公告)号：US20200027990A1

公开(公告)日：2020-01-23

申请号：US16587921

申请日：2019-09-30

Applicant: Micron Technology, Inc.

Inventor： Gurtej S. Sandhu

IPC: H01L29/786 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L27/105 ,  H01L21/8234 ,  B82Y10/00 ,  H01L27/12 ,  H01L29/24 ,  H01L29/40 ,  H01L29/423

Abstract: A semiconductor device structure is disclosed. The semiconductor device structure includes a mesa extending above a substrate. The mesa has a channel region between a first side and second side of the mesa. A first gate is on a first side of the mesa, the first gate comprising a first gate insulator and a first gate conductor comprising graphene overlying the first gate insulator. The gate conductor may comprise graphene in one or more monolayers. Also disclosed are a method for fabricating the semiconductor device structure; an array of vertical transistor devices, including semiconductor devices having the structure disclosed; and a method for fabricating the array of vertical transistor devices.

公开(公告)号：US10515996B2

公开(公告)日：2019-12-24

申请号：US15877064

申请日：2018-01-22

Applicant: Micron Technology, Inc.

Inventor： Witold Kula ,  Wayne I. Kinney ,  Gurtej S. Sandhu

IPC: H01L27/22 ,  H01L43/12 ,  H01L43/08 ,  G11C11/16 ,  H01L43/02 ,  H01L43/10

Abstract: A magnetic cell core includes a seed region with a plurality of magnetic regions and a plurality of nonmagnetic regions thereover. The seed region provides a template that enables formation of an overlying nonmagnetic region with a microstructure that enables formation of an overlying free region with a desired crystal structure. The free region is disposed between two nonmagnetic regions, which may both be configured to induce surface/interface magnetic anisotropy. The structure is therefore configured to have a high magnetic anisotropy strength, a high energy barrier ratio, high tunnel magnetoresistance, a low programming current, low cell-to-cell electrical resistance variation, and low cell-to-cell variation in magnetic properties. Methods of fabrication, memory arrays, memory systems, and electronic systems are also disclosed.