公开(公告)号：US10755755B2

公开(公告)日：2020-08-25

申请号：US16109628

申请日：2018-08-22

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Theodore T. Pekny ,  Jae-Kwan Park ,  Violante Moschiano ,  Michele Incarnati ,  Luca de Santis

IPC: G06F12/02 ,  G11C7/22 ,  G11C16/26 ,  G11C16/32

Abstract: Apparatuses and methods for performing concurrent memory access operations for different memory planes are disclosed herein. An example apparatus may include a memory array having a plurality of memory planes. Each of the plurality of memory planes comprises a plurality of memory cells. The apparatus may further include a controller configured to receive a group of memory command and address pairs. Each memory command and address pair of the group of memory command and address pairs may be associated with a respective memory plane of the plurality of memory planes. The internal controller may be configured to concurrently perform memory access operations associated with each memory command and address pair of the group of memory command and address pairs regardless of page types associated with the pairs of the group (e.g., even if two or more of the memory command and address pairs may be associated with different page types).

公开(公告)号：US20190034257A1

公开(公告)日：2019-01-31

申请号：US16148947

申请日：2018-10-01

Applicant: MICRON TECHNOLOGY INC.

Inventor： Jae-Kwan Park

IPC: G06F11/07 ,  G11C7/10 ,  G11C7/06 ,  G11C29/24

Abstract: Apparatuses and methods for comparing a sense current representative of a number of failing memory cells of a group of memory cells and a reference current representative of a reference number of failing memory cells is provided. One such apparatus includes a comparator configured to receive the sense current and to receive the reference current. The comparator includes a sense current buffer configured to buffer the sense current and the comparator is further configured to provide an output signal having a logic level indicative of a result of the comparison.

公开(公告)号：US10083727B2

公开(公告)日：2018-09-25

申请号：US15614072

申请日：2017-06-05

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Theodore T. Pekny ,  Jae-Kwan Park ,  Violante Moschiano ,  Michele Incarnati ,  Luca de Santis

IPC: G06F12/02 ,  G11C7/22 ,  G11C16/26 ,  G11C16/32

CPC classification number: G11C7/22 ,  G11C16/26 ,  G11C16/32 ,  G11C2207/2209

Abstract: Apparatuses and methods for performing concurrent memory access operations for different memory planes are disclosed herein. An example apparatus may include a memory array having a plurality of memory planes. Each of the plurality of memory planes comprises a plurality of memory cells. The apparatus may further include a controller configured to receive a group of memory command and address pairs. Each memory command and address pair of the group of memory command and address pairs may be associated with a respective memory plane of the plurality of memory planes. The internal controller may be configured to concurrently perform memory access operations associated with each memory command and address pair of the group of memory command and address pairs regardless of page types associated with the pairs of the group (e.g., even if two or more of the memory command and address pairs may be associated with different page types).

公开(公告)号：US09870280B2

公开(公告)日：2018-01-16

申请号：US15139054

申请日：2016-04-26

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jae-Kwan Park

IPC: G11C7/00 ,  G11C29/00 ,  G06F11/07 ,  G11C7/06 ,  G11C29/24 ,  G11C7/10

CPC classification number: G06F11/079 ,  G06F11/0727 ,  G06F11/0751 ,  G11C7/062 ,  G11C7/065 ,  G11C7/1057 ,  G11C7/1063 ,  G11C29/24 ,  G11C2207/063

Abstract: Apparatuses and methods for comparing a sense current representative of a number of failing memory cells of a group of memory cells and a reference current representative of a reference number of failing memory cells is provided. One such apparatus includes a comparator configured to receive the sense current and to receive the reference current. The comparator includes a sense current buffer configured to buffer the sense current and the comparator is further configured to provide an output signal having a logic level indicative of a result of the comparison.

公开(公告)号：US20170270976A1

公开(公告)日：2017-09-21

申请号：US15610281

申请日：2017-05-31

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jae-Kwan Park

IPC: G11C7/02 ,  G11C16/10 ,  G11C16/34 ,  G11C16/04

CPC classification number: G11C7/02 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/3427

Abstract: Apparatuses and methods for providing a program voltage responsive to a voltage determination are described. An example apparatus includes a memory array comprising a plurality of access lines. The example apparatus further includes a memory access circuit coupled to the memory array. The memory access circuit is configured to, during a memory program operation, provide an inhibit voltage to the plurality of access lines. The memory access circuit is further configured to, during the memory program operation, provide a program voltage to a target access line of the plurality of access lines responsive to a determination that an access line of the plurality of access lines has a voltage equal to or greater than a threshold voltage. The threshold voltage is less than the inhibit voltage.

公开(公告)号：US09691452B2

公开(公告)日：2017-06-27

申请号：US14461152

申请日：2014-08-15

Applicant: Micron Technology, Inc.

Inventor： Theodore T. Pekny ,  Jae-Kwan Park ,  Violante Moschiano ,  Michele Incarnati ,  Luca de Santis

IPC: G06F3/06 ,  G06F12/00 ,  G11C7/22 ,  G11C16/26 ,  G11C16/32

CPC classification number: G11C7/22 ,  G11C16/26 ,  G11C16/32 ,  G11C2207/2209

Abstract: Apparatuses and methods for performing concurrent memory access operations for different memory planes are disclosed herein. An example apparatus may include a memory array having a plurality of memory planes. Each of the plurality of memory planes comprises a plurality of memory cells. The apparatus may further include a controller configured to receive a group of memory command and address pairs. Each memory command and address pair of the group of memory command and address pairs may be associated with a respective memory plane of the plurality of memory planes. The internal controller may be configured to concurrently perform memory access operations associated with each memory command and address pair of the group of memory command and address pairs regardless of page types associated with the pairs of the group (e.g., even if two or more of the memory command and address pairs may be associated with different page types).

公开(公告)号：US09672875B2

公开(公告)日：2017-06-06

申请号：US14165389

申请日：2014-01-27

Applicant: Micron Technology, Inc.

Inventor： Jae-Kwan Park

IPC: G11C16/04 ,  G11C16/06 ,  G11C7/02 ,  G11C16/10 ,  G11C16/34

CPC classification number: G11C7/02 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/3427

Abstract: Apparatuses and methods for providing a program voltage responsive to a voltage determination are described. An example apparatus includes a memory array comprising a plurality of access lines. The example apparatus further includes a memory access circuit coupled to the memory array. The memory access circuit is configured to, during a memory program operation, provide an inhibit voltage to the plurality of access lines. The memory access circuit is further configured to, during the memory program operation, provide a program voltage to a target access line of the plurality of access lines responsive to a determination that an access line of the plurality of access lines has a voltage equal to or greater than a threshold voltage. The threshold voltage is less than the inhibit voltage.

公开(公告)号：US20160239367A1

公开(公告)日：2016-08-18

申请号：US15139054

申请日：2016-04-26

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jae-Kwan Park

IPC: G06F11/07 ,  G11C7/06

CPC classification number: G06F11/079 ,  G06F11/0727 ,  G06F11/0751 ,  G11C7/062 ,  G11C7/065 ,  G11C7/1057 ,  G11C7/1063 ,  G11C29/24 ,  G11C2207/063

Abstract: Apparatuses and methods for comparing a sense current representative of a number of failing memory cells of a group of memory cells and a reference current representative of a reference number of failing memory cells is provided. One such apparatus includes a comparator configured to receive the sense current and to receive the reference current. The comparator includes a sense current buffer configured to buffer the sense current and the comparator is further configured to provide an output signal having a logic level indicative of a result of the comparison.