公开(公告)号：US20210055981A1

公开(公告)日：2021-02-25

申请号：US16545721

申请日：2019-08-20

Applicant: Micron Technology, Inc.

Inventor： Daniel S. Miller ,  Kevin G. Werhane ,  Yoshinori Fujiwara ,  Christopher G. Wieduwilt ,  Jason M. Johnson ,  Minoru Someya

IPC: G06F11/07 ,  G11C17/16

Abstract: An example fuse error detection circuit configured to receive a first data set from a fuse array during a first fuse data broadcast and to encode the first data set to provide first signature data. The fuse error detection circuit is further configured to receive a second data set from the fuse array during a second fuse data broadcast and to encode the second data set to provide second signature data. The fuse error detection circuit is further configured to compare the first signature data and the second signature data and to provide a match indication having a value based on the comparison between the first signature data and the second signature data.

公开(公告)号：US10896704B2

公开(公告)日：2021-01-19

申请号：US16692306

申请日：2019-11-22

Applicant: Micron Technology, Inc.

Inventor： Jason M. Johnson ,  Jung-Hwa Choi

IPC: G11C11/4076 ,  G11C11/408 ,  G11C7/10 ,  G11C7/22

Abstract: An apparatus includes: a master die; one or more slave dies; a ZQ resister between a first node and a second node coupled to a voltage terminal; a ZQ pad coupled to each of the first node of the ZQ resister, the master die and the one or more slave dies; and a calibration channel electrically coupling the master die and the one or more slave dies, the calibration channel configured to communicate signals between the master die and the one or more slave dies for coordinating access to the ZQ pad across the master die and the one or more slave dies.

公开(公告)号：US10439612B1

公开(公告)日：2019-10-08

申请号：US16104374

申请日：2018-08-17

Applicant: Micron Technology, Inc.

Inventor： Jason M. Johnson

IPC: H03K19/00 ,  G11C7/10

Abstract: Systems and methods for performing an efficient ZQ calibration are provided herein. The described techniques use non-linearity compensation circuitry configured to compensate for a non-linear relationship between variation in a plurality of ZQ calibration codes and corresponding resistance variations, by adjusting either: a magnitude of the adjustment to the calibration step, the ZQCODE to an alternative ZQCODE, or both the magnitude of the adjustment to the calibration step and the ZQCODE to the alternative ZQCODE.

公开(公告)号：US10205451B1

公开(公告)日：2019-02-12

申请号：US15882723

申请日：2018-01-29

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jason M. Johnson

IPC: H03K19/00 ,  G11C8/10

Abstract: Methods and apparatuses are provided for dynamic step size for impedance calibration of a semiconductor device. An example apparatus includes a resistor, and a chip including a driver impedance calibration circuit configured to determine an impedance of the driver based on an impedance of the resistor. During a calibration operation, the driver impedance calibration circuit is configured to adjust an impedance code that controls an impedance of the driver to provide a next impedance code based on a comparison of a driver output voltage with a reference voltage. An adjustment step size of the impedance code is determined based on a value of the impedance code.

公开(公告)号：US11776612B2

公开(公告)日：2023-10-03

申请号：US17545966

申请日：2021-12-08

Applicant: Micron Technology, Inc.

Inventor： James S. Rehmeyer ,  Jason M. Johnson ,  Joo-Sang Lee

IPC: G11C11/406 ,  G06F11/30

CPC classification number: G11C11/40626 ,  G06F11/3037 ,  G06F11/3058 ,  G11C11/40607 ,  G11C11/40622

Abstract: Memory devices, systems, and associated methods with per die temperature-compensated refresh control, and associated methods, are disclosed herein. In one embodiment, a memory device includes a plurality of memory cells and a sensor configured to measure a temperature of the memory device. The memory device determines a frequency at which it is receiving refresh commands. The memory device is further configured to skip refresh operations of the memory cells based, at least in part, on the determination and on the temperature of the memory device.

公开(公告)号：US11645134B2

公开(公告)日：2023-05-09

申请号：US16545721

申请日：2019-08-20

Applicant: Micron Technology, Inc.

Inventor： Daniel S. Miller ,  Kevin G. Werhane ,  Yoshinori Fujiwara ,  Christopher G. Wieduwilt ,  Jason M. Johnson ,  Minoru Someya

IPC: G06F11/00 ,  G06F11/07 ,  G11C17/16 ,  H03K19/21

CPC classification number: G06F11/0751 ,  G06F11/0727 ,  G11C17/16 ,  H03K19/21

Abstract: An example fuse error detection circuit configured to receive a first data set from a fuse array during a first fuse data broadcast and to encode the first data set to provide first signature data. The fuse error detection circuit is further configured to receive a second data set from the fuse array during a second fuse data broadcast and to encode the second data set to provide second signature data. The fuse error detection circuit is further configured to compare the first signature data and the second signature data and to provide a match indication having a value based on the comparison between the first signature data and the second signature data.

公开(公告)号：US20220156148A1

公开(公告)日：2022-05-19

申请号：US17591362

申请日：2022-02-02

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yoshinori Fujiwara ,  Vivek Kotti ,  Christopher G. Wieduwilt ,  Jason M. Johnson ,  Kevin G. Werhane

IPC: G06F11/10 ,  G11C11/408

Abstract: Apparatuses, systems, and methods for error correction. A memory device may have a number of memory cells each of which stores a bit of information. One or more error correction code (ECC) may be used to determine if the bits of information contain any errors. To mitigate the effects of failures of adjacent memory cells, the information may be divided into a first group and a second group, where each group contains information from memory cells which are non-adjacent to other memory cells of that group. Each group of information may include data bits and parity bits used to correct those data bits. For example, as part of a read operation, a first ECC circuit may receive information from even numbered memory cells, while a second ECC circuit may receive information from odd numbered memory cells.

公开(公告)号：US11263078B2

公开(公告)日：2022-03-01

申请号：US16748554

申请日：2020-01-21

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yoshinori Fujiwara ,  Vivek Kotti ,  Christopher G. Wieduwilt ,  Jason M. Johnson ,  Kevin G. Werhane

IPC: G06F11/00 ,  G06F11/10 ,  G11C11/408 ,  G11C11/4096

Abstract: Apparatuses, systems, and methods for error correction. A memory device may have a number of memory cells each of which stores a bit of information. One or more error correction code (ECC) may be used to determine if the bits of information contain any errors. To mitigate the effects of failures of adjacent memory cells, the information may be divided into a first group and a second group, where each group contains information from memory cells which are non-adjacent to other memory cells of that group. Each group of information may include data bits and parity bits used to correct those data bits. For example, as part of a read operation, a first ECC circuit may receive information from even numbered memory cells, while a second ECC circuit may receive information from odd numbered memory cells.

公开(公告)号：US11183260B1

公开(公告)日：2021-11-23

申请号：US17098865

申请日：2020-11-16

Applicant: Micron Technology, Inc.

Inventor： Yoshinori Fujiwara ,  Dave Jefferson ,  Jason M. Johnson ,  Vivek Kotti ,  Minoru Someya ,  Toru Ishikawa ,  Kevin G. Werhane

IPC: G11C29/14 ,  G11C29/46 ,  G11C17/16 ,  G11C7/10

Abstract: Memory devices are disclosed. A memory device may include a number of fuses and a number of transmit lines configured to transmit data from the number of fuses. The memory device may also include a number of monitoring circuits. Each monitoring circuit of the number of monitoring circuits is coupled to a transmit line of the number of transmit lines. Each monitoring circuit comprises logic configured to receive the data from the number fuses via the transmit line. The logic is further configured to generate a result responsive to the data and indicative of pass/fail status of the transmit line. Associated methods and systems are also disclosed.

公开(公告)号：US20210200629A1

公开(公告)日：2021-07-01

申请号：US16748554

申请日：2020-01-21

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yoshinori Fujiwara ,  Vivek Kotti ,  Christopher G. Wieduwilt ,  Jason M. Johnson ,  Kevin G. Werhane

IPC: G06F11/10 ,  G11C11/408

Abstract: Apparatuses, systems, and methods for error correction. A memory device may have a number of memory cells each of which stores a bit of information. One or more error correction code (ECC) may be used to determine if the bits of information contain any errors. To mitigate the effects of failures of adjacent memory cells, the information may be divided into a first group and a second group, where each group contains information from memory cells which are non-adjacent to other memory cells of that group. Each group of information may include data bits and parity hits used to correct those data bits. For example, as part of a read operation, a first ECC circuit may receive information from even numbered memory cells, while a second ECC circuit may receive information from odd numbered memory cells.