公开(公告)号：US10937517B1

公开(公告)日：2021-03-02

申请号：US16685186

申请日：2019-11-15

Applicant: Micron Technology, Inc.

Inventor： Eric J. Rich-Plotkin ,  Christopher G. Wieduwilt ,  Boon Hor Lam ,  Greg S. Hendrix ,  Shawn M. Hilde ,  Jiyun Li ,  Dennis G. Montierth

IPC: G11C7/00 ,  G11C29/30 ,  G11C29/12 ,  G11C29/02 ,  H03M13/29 ,  G11C11/56 ,  G11C29/44

Abstract: An exemplary memory includes a memory cell array configured to store a plurality of data bits each associated with a respective column plane, and an input/output circuit including a compression circuit configured to provide error data based on a comparison between a bit of the plurality of data bits received from the memory cell array and an expected value and based on a respective column plane of the memory cell array with which the bit is associated. The compression circuit is further configured to encode a column plane error code based on the error data for provision to a data terminal.

公开(公告)号：US20200349995A1

公开(公告)日：2020-11-05

申请号：US16936297

申请日：2020-07-22

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Michael A. Shore ,  Jiyun Li

IPC: G11C11/406 ,  G11C11/407 ,  G11C11/4076

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for managing access counts of wordlines of a memory. Repeated access to an aggressor wordline may cause increased data degradation in nearby victim wordlines of the memory. The access count of a given wordline may be stored in counter memory cells positioned along that wordline. When the wordline is accessed, the counter memory cells may be read out to refresh circuit, which may determine the access count based on the values stored in the counter memory cells. If the access count is below a threshold, the access count may be incremented and written back to the counter memory cells. If the access count is above the threshold, the refresh circuit may signal that the accessed wordline is an aggressor, and may reset the value of the access count before writing it back to the counter memory cells.

公开(公告)号：US20250022505A1

公开(公告)日：2025-01-16

申请号：US18743561

申请日：2024-06-14

Applicant: Micron Technology, Inc.

Inventor： Jiyun Li

IPC: G11C11/4096 ,  G11C11/4094 ,  G11C11/4099

Abstract: A semiconductor device includes a column select circuit coupled to a complementary pair of bitlines. The column select circuit includes a pair of p-type transistors each coupled in series with a respective one of the complementary pair of bitlines and configured to provide a voltage on the respective one of the complementary pair of bitlines to a respective one of a complementary pair of local input/output (LIO) lines in response to a column select signal. The semiconductor device further includes a LIO circuit comprising a pair of transistors cross-coupled between the complementary pair of LIO lines. The pair of transistors is configured to transition the complementary pair of LIO lines to complementary values based on values provided on the complementary pair of bitlines.

公开(公告)号：US11984148B2

公开(公告)日：2024-05-14

申请号：US17470883

申请日：2021-09-09

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  Jason M. Brown ,  Nathaniel J. Meier ,  Timothy B. Cowles ,  Jiyun Li

IPC: G11C11/406 ,  G11C11/408

CPC classification number: G11C11/40611 ,  G11C11/4085 ,  G11C11/4087

Abstract: The address of victim rows may be determined based on rows that are accessed in a memory. The victim addresses may be stored and associated with a count for every time a victim row is “victimized.” When the count for a victim row reaches a threshold, the victim row may be refreshed to preserve data stored in the row. After the victim row has been refreshed, the count may be reset. When a victim row is accessed, the count may also be reset. The counts may be adjusted for closer victim rows (e.g., +/−1) at a faster rate than counts for more distant victim rows (e.g., +/−2). This may cause closer victim rows to be refreshed at a higher rate than more distant victim rows.

公开(公告)号：US20220270668A1

公开(公告)日：2022-08-25

申请号：US17184345

申请日：2021-02-24

Applicant: Micron Technology, Inc.

Inventor： Jiyun Li ,  Toby D. Robbs

IPC: G11C11/4097 ,  G11C11/408 ,  G11C11/4096

Abstract: A memory device may include a memory array having a plurality of memory cells and a first column plane having multiple column select lines. The first column select lines of the first column plane may access a first set of the memory cells associated with the first column plane. Additionally, the memory device may include a second column plane having a multiple column select lines to access a second set of the memory cells associated with the second column plane. The memory device may also include a column select line shared between the first column plane and the second column plane. The column select line may access a third set of the memory cells associated with the first column plane and a fourth set of the memory cells associated with the second column plane.

公开(公告)号：US20220216218A1

公开(公告)日：2022-07-07

申请号：US17141426

申请日：2021-01-05

Applicant: Micron Technology, Inc.

Inventor： Yuan He ,  Jiyun Li

IPC: H01L27/108 ,  G11C11/4091 ,  G11C11/4093 ,  G11C11/4094 ,  G11C11/4096

Abstract: Some embodiments include an integrated assembly having a memory array over a base. The memory array includes a three-dimensional arrangement of memory cells. Sense amplifiers are associated with the base and are directly under the memory array. Vertically-extending digit lines pass through the arrangement of the memory cells and are coupled with the sense amplifiers. Some embodiments include an integrated assembly having a memory bank containing 64 memory chunks arranged in a 16×4 configuration. Some embodiments include an integrated assembly having a memory bank which contains 512 megabytes divided amongst 64 memory chunks which each have 8 megabytes. The 64 memory chunks are arranged in a configuration having multiple rows which each contain a two or more of the memory chunks.

公开(公告)号：US11257535B2

公开(公告)日：2022-02-22

申请号：US16936297

申请日：2020-07-22

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Michael A. Shore ,  Jiyun Li

IPC: G11C11/406 ,  G11C11/4076 ,  G11C11/407

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for managing access counts of wordlines of a memory. Repeated access to an aggressor wordline may cause increased data degradation in nearby victim wordlines of the memory. The access count of a given wordline may be stored in counter memory cells positioned along that wordline. When the wordline is accessed, the counter memory cells may be read out to refresh circuit, which may determine the access count based on the values stored in the counter memory cells. If the access count is below a threshold, the access count may be incremented and written back to the counter memory cells. If the access count is above the threshold, the refresh circuit may signal that the accessed wordline is an aggressor, and may reset the value of the access count before writing it back to the counter memory cells.

公开(公告)号：US20220012125A1

公开(公告)日：2022-01-13

申请号：US16926559

申请日：2020-07-10

Applicant: Micron Technology, Inc.

Inventor： Jiyun Li ,  Johnathan L. Gossi

IPC: G06F11/10 ,  G06F11/07 ,  G06F11/30 ,  G11C29/10

Abstract: Methods, systems, and devices for a compression method for defect visibility in a memory device are described. A memory device may identify one or more errors associated with a set of memory cells of a memory array in the device based on a first set of data associated with the first set of memory cells. The memory device may generate an indication of a location of the one or more errors in the first set of memory cells and compress the first set of data to generate an error flag based on identifying the one or more errors. The memory device may output the error flag and the indication of the location based on generating the error flag and the indication.

公开(公告)号：US11158364B2

公开(公告)日：2021-10-26

申请号：US16428625

申请日：2019-05-31

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  Jason M. Brown ,  Nathaniel J. Meier ,  Timothy B. Cowles ,  Jiyun Li

IPC: G11C7/00 ,  G11C11/406 ,  G11C11/408

Abstract: The address of victim rows may be determined based on rows that are accessed in a memory. The victim addresses may be stored and associated with a count for every time a victim row is “victimized.” When the count for a victim row reaches a threshold, the victim row may be refreshed to preserve data stored in the row. After the victim row has been refreshed, the count may be reset. When a victim row is accessed, the count may also be reset. The counts may be adjusted for closer victim rows (e.g., +/−1) at a faster rate than counts for more distant victim rows (e.g., +/−2). This may cause closer victim rows to be refreshed at a higher rate than more distant victim rows.

公开(公告)号：US11087819B2

公开(公告)日：2021-08-10

申请号：US16597694

申请日：2019-10-09

Applicant: Micron Technology, Inc.

Inventor： Timothy B. Cowles ,  Dean D. Gans ,  Jiyun Li ,  Nathaniel J. Meier ,  Randall J. Rooney

IPC: G11C7/00 ,  G11C11/406

Abstract: Memory devices and methods of operating memory devices in which refresh management operations can be scheduled on an as-needed basis for those memory portions where activity (e.g., activations in excess of a predetermined threshold) warrants a refresh management operation are disclosed. In one embodiment, an apparatus comprises a memory including a memory location, and circuitry configured to determine a count corresponding to a number of activations at the memory location, to schedule a refresh management operation for the memory location in response to the count exceeding a first predetermined threshold, and to decrease the count by an amount corresponding to the first predetermined threshold in response to executing the scheduled refresh management operation. The circuitry may be further configured to disallow, in response to determining that the count has reached a maximum permitted value, further activations at the memory location until after the count has been decreased.