公开(公告)号：US11069393B2

公开(公告)日：2021-07-20

申请号：US16431641

申请日：2019-06-04

Applicant: Micron Technology, Inc.

Inventor： Timothy B. Cowles ,  Jiyun Li ,  Beau D. Barry ,  Matthew D. Jenkinson ,  Nathaniel J. Meier ,  Michael A. Shore ,  Adam J. Grenzebach ,  Dennis G. Montierth

IPC: G11C7/00 ,  G11C11/406 ,  G11C11/408

Abstract: An apparatus may include a refresh control circuit with multiple timing circuits. The timing circuits may be used to control steal rates, e.g., the rate of refresh time slots dedicated to healing victim word lines of row hammers. The timing circuits may be controlled to allow independent adjustment of the steal rates for different victim word lines. Thus, different victim word lines may be refreshed at different rates and the different rates may be independent of one another.

公开(公告)号：US11011215B1

公开(公告)日：2021-05-18

申请号：US16721373

申请日：2019-12-19

Applicant: Micron Technology, Inc.

Inventor： Jonathan S. Parry ,  Michael A. Shore

IPC: G06F13/16 ,  G11C11/406

Abstract: Methods, apparatuses, and systems related to scheduling internal operations are described. An apparatus detects a condition associated with repeated accesses to a memory address and/or region. In response to detection of the condition, the apparatus generates a scheduling output that secures a scheduled duration of inactivity for commanded operations. The apparatus initiates execution of one or more internal operations during the scheduled duration.

公开(公告)号：US20190019553A1

公开(公告)日：2019-01-17

申请号：US16005493

申请日：2018-06-11

Applicant: Micron Technology, Inc.

Inventor： Scott J. Derner ,  Michael A. Shore

IPC: G11C14/00 ,  G11C11/22 ,  G11C11/4091 ,  H01L27/11507 ,  H01L27/108 ,  H01L49/02 ,  G11C11/4096 ,  G11C11/4097

Abstract: Apparatuses and methods for memory including ferroelectric memory cells and dielectric memory cells are disclosed. The apparatus includes a first memory cell including first and second ferroelectric capacitors configured to store charges representing complementary logical values, a second memory cell including first and second dielectric capacitors configured to store charges representing complementary logical values, a first bit line selectably coupled to the first ferroelectric capacitor of the first memory cell and to the first dielectric capacitor of the second memory cell, a second bit line selectably coupled to the second ferroelectric capacitor of the first memory cell and to the second dielectric capacitor of the second memory cell, and a sense amplifier coupled to the first and second bit lines.

公开(公告)号：US10127971B1

公开(公告)日：2018-11-13

申请号：US15583023

申请日：2017-05-01

Applicant: Micron Technology, Inc.

Inventor： Scott J. Derner ,  Huy T. Vo ,  Patrick Mullarkey ,  Jeffrey P. Wright ,  Michael A. Shore

IPC: G11C11/4091 ,  G11C11/406 ,  G11C11/4072 ,  G11C11/4094 ,  G11C11/4096

Abstract: Systems and methods are provided for implementing an array rest mode. An example system includes at least one mode register configured to enable an array reset mode, a memory cell array including one or more sense amplifiers, and control logic. Each of the one or more sense amplifier may include at least a first terminal coupled to a first bit line and a second terminal coupled to a second bit line. The control logic may be coupled to the memory cell array, and in communication with the at least one mode register. The control logic may be configured to drive, in response to array reset mode being enabled, each of the first and second terminals of the sense amplifier to a bit-line precharge voltage that corresponds to a bit value to be written to respective memory cells associated with each of the first and second bit lines.

公开(公告)号：US20230020753A1

公开(公告)日：2023-01-19

申请号：US17305878

申请日：2021-07-16

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yoshinori Fujiwara ,  Harish V. Gadamsetty ,  Gary Howe ,  Dennis G. Montierth ,  Michael A. Shore ,  Jason M. Johnson

IPC: G11C11/406 ,  G11C11/408 ,  G11C29/00 ,  G11C29/44

Abstract: Apparatuses, systems, and methods for refresh address masking. A memory device may refresh word lines as part of refresh operation by cycling through the word lines in a sequence. However, it may be desirable to avoid activating certain word lines (e.g., because they are defective). Refresh masking logic for each bank may include a fuse latch which stores a selected address associated with a word line to avoid. When a refresh address is generated it may be compared to the selected address. If there is a match, a refresh stop signal may be activated, which may prevent refreshing of the word line(s).

公开(公告)号：US20220293169A1

公开(公告)日：2022-09-15

申请号：US17301970

申请日：2021-04-20

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Nathaniel J. Meier ,  Michael A. Shore

IPC: G11C11/406 ,  G11C11/408 ,  G11C11/4076

Abstract: Apparatuses, systems, and methods for controller directed targeted refresh operations. A memory may be coupled to a controller. The memory may identify aggressor addresses based on sampled addresses. The addresses may be sampled based on internal timing logic of the memory and also based on a sampling command received from the controller. The memory may also receive a controller identified aggressor address from the controller. The memory may refresh one or more victim word lines of the identified (either by the memory or the controller) aggressor addresses as part of a targeted refresh operation. Victims of controller identified aggressor addresses may be refreshed before memory identified aggressor addresses.

公开(公告)号：US11069384B2

公开(公告)日：2021-07-20

申请号：US16372000

申请日：2019-04-01

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Shinichi Miyatake ,  Michael A. Shore ,  Adam J. Grenzebach

IPC: G11C11/4091 ,  G11C7/08

Abstract: Apparatuses and methods for compensation of sense amplifiers, for example, threshold voltage compensation, are disclosed. Prime memory sense amplifiers used for accessing prime memory and redundant memory sense amplifiers used for accessing redundant memory are concurrently compensated while determining whether a memory address is remapped from prime memory to redundant memory. Following the determination, sense amplifiers (e.g., prime memory sense amplifiers and/or redundant memory sense amplifiers) that are not used for accessing the memory corresponding to the memory address are precharged.

公开(公告)号：US10600472B2

公开(公告)日：2020-03-24

申请号：US16105889

申请日：2018-08-20

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Scott J. Derner ,  Huy T. Vo ,  Patrick Mullarkey ,  Jeffrey P. Wright ,  Michael A. Shore

IPC: G11C11/4091 ,  G11C11/406 ,  G11C11/4072 ,  G11C11/4094 ,  G11C11/4096

Abstract: Systems and methods are provided for implementing an array reset mode. An example system includes at least one mode register configured to enable an array reset mode, a memory cell array including one or more sense amplifiers, and control logic. Each of the one or more sense amplifier may include at least a first terminal coupled to a first bit line and a second terminal coupled to a second bit line. The control logic may be coupled to the memory cell array, and in communication with the at least one mode register. The control logic may be configured to drive, in response to array reset mode being enabled, each of the first and second terminals of the sense amplifier to a bit-line precharge voltage that corresponds to a bit value to be written to respective memory cells associated with each of the first and second bit lines.

公开(公告)号：US08868991B2

公开(公告)日：2014-10-21

申请号：US13867790

申请日：2013-04-22

Applicant: Micron Technology, Inc.

Inventor： Michael A. Shore

IPC: G11C29/00 ,  G11C29/44 ,  G11C29/38

CPC classification number: G11C29/44 ,  G11C29/36 ,  G11C29/38 ,  G11C29/4401 ,  G11C29/883 ,  G11C2229/723

Abstract: Testing systems and methods, as well as memory devices using such testing systems and methods, may facilitate testing of memory devices using a read-modify-write test procedure. One such testing system receives a signal indicative of at least some of a plurality of bits of data read from an address differing from each other, and then masks subsequent write operations at the same address. Therefore, any address at which the bits of read data do not all have the same value may be considered to be faulty. Failure data from the test can therefore be stored in the same array of memory cells that is being tested.

Abstract translation: 使用这种测试系统和方法的测试系统和方法以及存储器件可以使用读 - 修改 - 写测试程序来促进对存储器件的测试。 一个这样的测试系统接收指示从彼此不同的地址读取的多个数据位中的至少一些的信号，然后在相同的地址处屏蔽后续的写入操作。 因此，读取数据的比特并不都具有相同值的任何地址可能被认为是有缺陷的。 因此，测试中的故障数据可以存储在正在测试的同一阵列的存储单元中。

公开(公告)号：US20130232386A1

公开(公告)日：2013-09-05

申请号：US13867790

申请日：2013-04-22

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Michael A. Shore

IPC: G11C29/38

CPC classification number: G11C29/44 ,  G11C29/36 ,  G11C29/38 ,  G11C29/4401 ,  G11C29/883 ,  G11C2229/723

Abstract: Testing systems and methods, as well as memory devices using such testing systems and methods, may facilitate testing of memory devices using a read-modify-write test procedure. One such testing system receives a signal indicative of at least some of a plurality of bits of data read from an address differing from each other, and then masks subsequent write operations at the same address. Therefore, any address at which the bits of read data do not all have the same value may be considered to be faulty. Failure data from the test can therefore be stored in the same array of memory cells that is being tested.