公开(公告)号：US11635894B2

公开(公告)日：2023-04-25

申请号：US16488696

申请日：2019-03-15

Applicant: Micron Technology, Inc.

Inventor： Paolo Papa ,  Carminantonio Manganelli ,  Massimo Iaculo ,  Giuseppe D'Eliseo ,  Alberto Sassara

IPC: G06F3/06

Abstract: Disclosed in some examples are improvements to data placement architectures in NAND that provide additional data protection through an improved NAND data placement schema that allows for recovery from certain failure scenarios. The present disclosure stripes data diagonally across page lines and planes to enhance the data protection. Parity bits are stored in SLC blocks for extra protection until the block is finished writing and then the parity bits may be deleted.

公开(公告)号：US20230068324A1

公开(公告)日：2023-03-02

申请号：US17461469

申请日：2021-08-30

Applicant: Micron Technology, Inc.

Inventor： Lalla Fatima Drissi ,  Doriana Tardio ,  Giuseppe D'Eliseo ,  Giuseppe Ferrari

IPC: G06F3/06

Abstract: Methods, systems, and devices for memory operations are described. A memory system may write data to sequential physical addresses of the memory system based on receiving multiple write commands, where the sequential physical addresses may be associated with sequential logical addresses. Based on writing the data, the memory system may receive a read command for data stored in the memory system, where the read command may include a logical address. The memory system may determine a physical address of the memory system where the data is stored based on the received logical address, a last logical address written at the memory system, and a sequence number group associated with the last logical address. Based on determining the physical address, the memory system may read the data stored at the physical address.

公开(公告)号：US20220406388A1

公开(公告)日：2022-12-22

申请号：US17736902

申请日：2022-05-04

Applicant: Micron Technology, Inc.

Inventor： Umberto Siciliani ,  Tao Liu ,  Ting Luo ,  Dionisio Minopoli ,  Giuseppe D'Eliseo ,  Giuseppe Ferrari ,  Walter Di'Francesco ,  Antonino Pollio ,  Luigi Esposito ,  Anna Scalesse ,  Allison J. Olson ,  Anna Chiara Siviero

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26

Abstract: Methods, systems, and devices for setting switching for single-level cells (SLCs) are described. A memory system may receive an access command from a host. The access command may correspond to an SLC block or to a multiple-level cell block. If the access command corresponds to an SLC block, the memory system may modify the access command to include one or more bits indicating a setting to use for performing the access operation corresponding to the access command. The setting may define one or more operating parameters for performing the access operation. The memory system may use bits to indicate the setting that are used to indicate a page address for multiple-level cell blocks. The memory system may issue the access command to a memory device, which may perform the access operation using the setting indicated in the one or more bits included by the memory system.

公开(公告)号：US11520525B2

公开(公告)日：2022-12-06

申请号：US17315015

申请日：2021-05-07

Applicant: Micron Technology, Inc.

Inventor： Giuseppe D'Eliseo ,  Luca Porzio ,  Stephen Hanna

IPC: G06F3/06 ,  G06F12/10

Abstract: Methods, systems, and devices for integrating a pivot table in a logical-to-physical mapping of a memory system are described. The memory system may receive a read command and read a first entry of a first subset of mapping and a second entry of a second subset of mapping. The second entry may include at least a portion of a pivot table associated with physical addresses of a non-volatile memory device. The memory system may retrieve data from a physical address identified in the pivot table, rather than access a different portion of the logical-to-physical mapping. The memory system may transmit, to a host system, the data retrieved from the physical address identified in the pivot table.

公开(公告)号：US20220357884A1

公开(公告)日：2022-11-10

申请号：US17315015

申请日：2021-05-07

Applicant: Micron Technology, Inc.

Inventor： Giuseppe D'Eliseo ,  Luca Porzio ,  Stephen Hanna

IPC: G06F3/06 ,  G06F12/10

Abstract: Methods, systems, and devices for integrating a pivot table in a logical-to-physical mapping of a memory system are described. The memory system may receive a read command and read a first entry of a first subset of mapping and a second entry of a second subset of mapping. The second entry may include at least a portion of a pivot table associated with physical addresses of a non-volatile memory device. The memory system may retrieve data from a physical address identified in the pivot table, rather than access a different portion of the logical-to-physical mapping. The memory system may transmit, to a host system, the data retrieved from the physical address identified in the pivot table.

公开(公告)号：US11269545B2

公开(公告)日：2022-03-08

申请号：US16075464

申请日：2017-12-21

Applicant: Micron Technology, Inc.

Inventor： Eric Kwok Fung Yuen ,  Giuseppe Ferrari ,  Massimo Iaculo ,  Lalla Fatima Drissi ,  Xinghui Duan ,  Giuseppe D'Eliseo

IPC: G06F3/06 ,  G06F12/02

Abstract: Devices and techniques for NAND logical-to-physical table region tracking are described herein. A write request, including a logical page and data to be written at the logical page, is received at a controller of a NAND device. The NAND controller may then establish an entry in a logical-to-physical (L2P) mapping table between the logical page and a physical page of a physical block of the NAND device to which the data is written. Here, the entry may be in a region of the L2P mapping table that is one of multiple regions. An indication of the region may be written in a data structure corresponding to the physical block.

公开(公告)号：US20210405726A1

公开(公告)日：2021-12-30

申请号：US17470506

申请日：2021-09-09

Applicant: Micron Technology, Inc.

Inventor： Giuseppe D'Eliseo ,  Xiangang Luo ,  Ting Luo ,  Jianmin Huang

IPC: G06F1/3206 ,  G06F12/06 ,  G06F12/02 ,  G06F1/3296

Abstract: Systems and methods are disclosed, including, in a storage system comprising control circuitry and a memory array having multiple groups of memory cells, storing a first physical-to-logical (P2L) data structure for a first physical area of a first group of memory cells in a second physical area of the first group of memory cells, such as when resuming operation from a low-power state, including an asynchronous power loss (APL). The first group of memory cells can include a super block of memory cells. A second P2L data structure for the second physical area of the first group of memory cells can be stored, such as in a metadata area of the second physical area and an address of the first P2L data structure can be stored in the second P2L data structure.

公开(公告)号：US11132044B2

公开(公告)日：2021-09-28

申请号：US16406779

申请日：2019-05-08

Applicant: Micron Technology, Inc.

Inventor： Giuseppe D'Eliseo ,  Xiangang Luo ,  Ting Luo ,  Jianmin Huang

IPC: G06F1/3206 ,  G06F12/06 ,  G06F12/02 ,  G06F1/3296

Abstract: Systems and methods are disclosed, including, in a storage system comprising control circuitry and a memory array having multiple groups of memory cells, storing a first physical-to-logical (P2L) data structure for a first physical area of a first group of memory cells in a second physical area of the first group of memory cells, such as when resuming operation from a low-power state, including an asynchronous power loss (APL). The first group of memory cells can include a super block of memory cells. A second P2L data structure for the second physical area of the first group of memory cells can be stored, such as in a metadata area of the second physical area, and an address of the first P2L data structure can be stored in the second P2L data structure.

公开(公告)号：US10108372B2

公开(公告)日：2018-10-23

申请号：US14605593

申请日：2015-01-26

Applicant: Micron Technology, Inc.

Inventor： Giuseppe D'Eliseo ,  Graziano Mirichigni ,  Danilo Caraccio ,  Luca Porzio ,  Antonino Pollio

IPC: G06F3/06 ,  G06F12/00

Abstract: Methods and apparatuses are disclosed for executing a plurality of queued tasks in a memory. One example apparatus includes a memory configured to be coupled to a host. The memory is also configured to receive a plurality of memory access requests, a status request, and an execution command from the host, and to execute one or more of the plurality of memory access requests responsive to the execution command from the host. The execution command includes a plurality of respective indications that correspond to each respective memory access request of the plurality of memory access requests and that indicate whether the host is requesting the memory to execute each respective memory access request.

公开(公告)号：US20240394183A1

公开(公告)日：2024-11-28

申请号：US18793378

申请日：2024-08-02

Applicant: Micron Technology, Inc.

Inventor： Lalla Fatima Drissi ,  Giuseppe D'Eliseo ,  Paolo Papa ,  Massimo Iaculo ,  Carminantonio Manganelli

IPC: G06F12/02 ,  G06F3/06

Abstract: Devices and techniques for corrupted storage portion recovery in a memory device are described herein. A failure event can be detected during a garbage collection operation on a collection of storage portions (e.g., pages) in a memory array. Here, members of the collection of storage portions are being moved from a former physical location to a new physical location by the garbage collection operation. A reference to a former physical location of a possibly corrupt storage portion in the collection of storage portions can be retrieved in response to the failure event. Here, the possibly corrupt storage portion has already been written to a new physical location as part of the garbage collection operation. The possibly corrupt storage portion can then be rewritten at the new physical location using data from the former physical location.