公开(公告)号：US20160012905A1

公开(公告)日：2016-01-14

申请号：US14326212

申请日：2014-07-08

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Kuo-Pin Chang ,  Chih-Shen Chang

IPC: G11C16/34 ,  G11C11/56

CPC classification number: G11C16/3427 ,  G11C11/5628 ,  G11C16/0483 ,  G11C2211/5622 ,  G11C2211/5648

Abstract: Common problems when programming 3D NAND Flash memory having alternating page orientation include the back-pattern effect and pattern-induced program disturb. Improved programming techniques may substantially reduce these problems and, in turn, increase precision when setting memory cells' threshold voltages. Provided are exemplary techniques that combine aspects of “by-word-line” programming and “by-page” programming. As such, each page may be programmed beginning with the memory cells that are closest to string select structures, and memory cells on multiple even or odd pages may be programmed substantially simultaneously.

Abstract translation: 编程具有交替页面取向的3D NAND闪存的常见问题包括背景图案效果和图案引起的程序干扰。 改进的编程技术可以显着地减少这些问题，并且在设置存储器单元的阈值电压时又提高精度。 提供了组合“逐字线”编程和“逐页”编程的方面的示例性技术。 这样，每个页面可以从最接近字符串选择结构的存储器单元开始编程，并且可以基本上同时编程多个偶数页或奇数页上的存储器单元。

公开(公告)号：US10811427B1

公开(公告)日：2020-10-20

申请号：US16387650

申请日：2019-04-18

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yu-Wei Jiang ,  Kuo-Pin Chang ,  Chieh-Fang Chen

IPC: H01L27/1158 ,  H01L21/762 ,  H01L29/417

Abstract: A semiconductor structure includes a substrate, conductive layers, dielectric layers, an isolation structure, a first memory structure, and a second memory structure. The conductive layers and the dielectric layers are interlaced and stacked on the substrate. The isolation structure is disposed on the substrate and through the conductive layers and the dielectric layers. Each of the first and second memory structures has a radius of curvature. The first and second memory structures penetrate through the conductive layers and the dielectric layers and are disposed on opposite sidewalls of the isolation structure. Each of the first and second memory structures includes protecting structures and a memory structure layer including a memory storage layer. The protecting structures are disposed at two ends of the memory storage layer, and an etching selectivity to the protecting structures is different from an etching selectivity to the memory storage layer.

公开(公告)号：US09490017B2

公开(公告)日：2016-11-08

申请号：US14643907

申请日：2015-03-10

Applicant: Macronix International Co., Ltd.

Inventor： Kuo-Pin Chang ,  Hang-Ting Lue ,  Wen-Wei Yeh

IPC: G11C11/34 ,  G11C16/04 ,  G11C16/14 ,  G11C16/10

CPC classification number: G11C16/14 ,  G11C16/0466 ,  G11C16/0475 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/3472

Abstract: A method is provided for operating a NAND array that includes a plurality of blocks of memory cells. A block of memory cells includes a plurality of NAND strings having channel lines between first string select switches and second string select switches. The plurality of NAND strings shares a set of word lines between the first and second string select switches. A channel-side erase voltage is applied to the channel lines through the first string select switches in a selected block. Word line-side erase voltages are applied to a selected subset of the set of word lines in the selected block to induce tunneling in memory cells coupled to the selected subset. Word line-side inhibit voltages are applied to an unselected subset of the set of word lines in the selected block to inhibit tunneling in memory cells coupled to the unselected subset.

Abstract translation: 提供了一种用于操作包括多个存储单元块的NAND阵列的方法。 存储单元块包括多个具有第一串选择开关和第二串选择开关之间的通道线的NAND串。 多个NAND串在第一和第二串选择开关之间共享一组字线。 通道侧擦除电压通过所选块中的第一串选择开关施加到通道线。 字线侧擦除电压被施加到所选块中所选择的字线集合的选定子集，以诱导耦合到所选子集的存储器单元中的隧穿。 字线侧抑制电压被施加到所选块中的字线组的未选择子集，以抑制耦合到未选择子集的存储器单元中的隧穿。

公开(公告)号：US20160247570A1

公开(公告)日：2016-08-25

申请号：US14723321

申请日：2015-05-27

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Kuo-Pin Chang ,  Hang-Ting Lue

IPC: G11C16/04 ,  G11C16/08

CPC classification number: G11C16/0483 ,  G11C16/08 ,  H01L27/11582

Abstract: A memory device includes a plurality of strings of memory cells. A plurality of stacks of conductive strips includes first upper strips configured as first string select lines for the strings in the plurality of strings, second upper strips configured as second string select lines for the strings in the plurality of strings, and intermediate strips configured as word lines for the strings in the plurality of strings. The memory device includes control circuitry coupled to the first string select lines and the second string select lines, and configured to select a particular string in the plurality of strings by applying a first turn-on voltage to a first string select line in the first string select lines coupled to the particular string, and a second turn-on voltage to a second string select line in the second string select lines coupled to the particular string.

Abstract translation: 存储器件包括多个存储单元串。 导电条的多个堆叠包括构成为多个串中的串的第一串选择线的第一上带，被配置为多个串中的串的第二串选择线的第二上带，以及配置为字的中间带 用于多个字符串中的字符串的行。 存储器件包括耦合到第一串选择线和第二串选择线的控制电路，并且被配置为通过向第一串中的第一串选择线施加第一导通电压来选择多个串中的特定串 选择耦合到特定串的线，以及第二接通电压到耦合到特定串的第二串选择线中的第二串选择线。

公开(公告)号：US09305653B1

公开(公告)日：2016-04-05

申请号：US14561630

申请日：2014-12-05

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chih-Chang Hsieh ,  Kuo-Pin Chang ,  Hang-Ting Lue

IPC: G11C16/04 ,  G11C16/14 ,  G11C11/56 ,  G11C16/26 ,  G11C16/24 ,  G11C16/34

CPC classification number: G11C16/3431 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0408 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C16/3459 ,  G11C2211/5621 ,  G11C2211/5648

Abstract: A method of operating a memory array is disclosed. The memory array includes a plurality of memory cells arranged in rows and columns, wherein a plurality of parallel memory strings correspond to respective ones of the columns, and a plurality of word lines are arranged orthogonal to the plurality of memory strings, each word line being connected to gate electrodes of a corresponding one of the rows of memory cells. The method includes performing a program operation that programs all of the memory cells on edge word lines located at opposite edges of the memory array, and that programs selected memory cells between the edge word lines in the memory array according to input data to be stored in the memory array. Each programmed memory cell has a threshold voltage at a program verify (PV) level.

Abstract translation: 公开了一种操作存储器阵列的方法。 存储器阵列包括以行和列排列的多个存储单元，其中多个并行存储器串对应于各个列，并且多个字线被布置为与多个存储器串正交，每个字线为 连接到存储器单元的相应行之一的栅电极。 该方法包括执行对位于存储器阵列的相对边缘的边缘字线上的所有存储单元进行编程的程序操作，并且根据要存储在存储器阵列中的输入数据在存储器阵列中的边缘字线之间编程所选存储单元 内存阵列。 每个编程的存储单元在程序验证（PV）级别具有阈值电压。