公开(公告)号：US10811427B1

公开(公告)日：2020-10-20

申请号：US16387650

申请日：2019-04-18

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yu-Wei Jiang ,  Kuo-Pin Chang ,  Chieh-Fang Chen

IPC: H01L27/1158 ,  H01L21/762 ,  H01L29/417

Abstract: A semiconductor structure includes a substrate, conductive layers, dielectric layers, an isolation structure, a first memory structure, and a second memory structure. The conductive layers and the dielectric layers are interlaced and stacked on the substrate. The isolation structure is disposed on the substrate and through the conductive layers and the dielectric layers. Each of the first and second memory structures has a radius of curvature. The first and second memory structures penetrate through the conductive layers and the dielectric layers and are disposed on opposite sidewalls of the isolation structure. Each of the first and second memory structures includes protecting structures and a memory structure layer including a memory storage layer. The protecting structures are disposed at two ends of the memory storage layer, and an etching selectivity to the protecting structures is different from an etching selectivity to the memory storage layer.

公开(公告)号：US10685971B2

公开(公告)日：2020-06-16

申请号：US16159753

申请日：2018-10-15

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yu-Wei Jiang ,  Chieh-Fang Chen ,  Jia-Rong Chiou

IPC: H01L21/76 ,  H01L21/822 ,  H01L21/8234 ,  H01L27/11521 ,  H01L27/11556 ,  H01L27/11568 ,  H01L27/11582 ,  G11C5/02 ,  G11C5/06 ,  G11C5/12 ,  G11C16/04

Abstract: A 3D memory device includes a substrate, a plurality of conductive layers, a plurality of insulating layers, a memory layer and a channel layer. The insulating layers are alternately stacked with the conductive layers on the substrate to form a multi-layers stacking structure, wherein the multi-layers stacking structure has at least one trench penetrating through the insulating layers and the conductive layers. The memory layer covers on the multi-layers stacking structure and at least extends onto a sidewall of the trench. The cannel layer covers on the memory layer and includes an upper portion adjacent to an opening of the trench, a lower portion adjacent to a bottom of the trench and a string portion disposed on the sidewall, wherein the string portion connects the upper portion with the lower portion and has a doping concentration substantially lower than that of the upper portion and lower portion.

公开(公告)号：US09330764B2

公开(公告)日：2016-05-03

申请号：US14305782

申请日：2014-06-16

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Lee-Yin Lin ,  Teng-Hao Yeh ,  Chih-Wei Hu ,  Chieh-Fang Chen

IPC: G11C11/34 ,  G11C16/08 ,  H01L21/768 ,  H01L21/266

CPC classification number: G11C16/08 ,  G11C8/14 ,  H01L21/266 ,  H01L21/28052 ,  H01L21/76895 ,  H01L27/11573 ,  H01L27/11578

Abstract: A device, such as an integrated circuit including memory, includes an array of memory cells on a substrate. A row/column line, such as a local word line or local bit line, is disposed in the array. The row/column line includes a pass transistor structure comprising a semiconductor strip in a first patterned layer over the substrate. The semiconductor strip includes a semiconductor channel body, a contact region on one side of the semiconductor channel body, and an extension on another side of the semiconductor channel body, which reaches into the memory cells in the array. A select line in a second patterned layer crossing the semiconductor channel body is provided. The pass transistor structure can be implemented in a fanout structure for row/column lines in the array.

Abstract translation: 诸如包括存储器的集成电路的装置包括衬底上的存储器单元的阵列。 行/列行，例如本地字线或局部位线，被布置在阵列中。 行/列线包括传输晶体管结构，其包括在衬底上的第一图案化层中的半导体条。 半导体条包括半导体通道主体，半导体通道主体一侧的接触区域和半导体通道体的另一侧的延伸部分，其延伸到阵列中的存储单元中。 提供了与半导体通道体交叉的第二图案化层中的选择线。 传输晶体管结构可以在阵列中的行/列线的扇出结构中实现。

公开(公告)号：US08772747B2

公开(公告)日：2014-07-08

申请号：US13867525

申请日：2013-04-22

Applicant: Macronix International Co., Ltd.

Inventor： Huai-Yu Cheng ,  Chieh-Fang Chen ,  Hsiang-Lan Lung ,  Yen-Hao Shih ,  Simone Raoux ,  Matthew J. Breitwisch

IPC: H01L47/00

CPC classification number: H01L47/00 ,  C23C14/06 ,  C23C14/0623 ,  C23C14/3414 ,  H01L21/06 ,  H01L27/24 ,  H01L45/144 ,  H01L45/1625

Abstract: A layer of phase change material with silicon or another semiconductor, or a silicon-based or other semiconductor-based additive, is formed using a composite sputter target including the silicon or other semiconductor, and the phase change material. The concentration of silicon or other semiconductor is more than five times greater than the specified concentration of silicon or other semiconductor in the layer being formed. For silicon-based additive in GST-type phase change materials, sputter target may comprise more than 40 at % silicon. Silicon-based or other semiconductor-based additives can be formed using the composite sputter target with a flow of reactive gases, such as oxygen or nitrogen, in the sputter chamber during the deposition.

Abstract translation: 使用包括硅或其它半导体的复合溅射靶和相变材料形成具有硅或另一半导体或硅基或其它基于半导体的添加剂的相变材料层。 硅或其他半导体的浓度比正在形成的层中规定浓度的硅或其它半导体的浓度高五倍以上。 对于GST型相变材料中的硅基添加剂，溅射靶可以包含超过40at％的硅。 可以在沉积期间使用复合溅射靶在溅射室中形成具有诸如氧或氮的反应气体流的硅基或其它基于半导体的添加剂。