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    Nested wrap-around memory access with fixed offset
    21.
    发明授权
    Nested wrap-around memory access with fixed offset 有权

    公开(公告)号：US10162751B2

    公开(公告)日：2018-12-25

    申请号：US15139252

    申请日：2016-04-26

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Kuen-Long Chang ,  Ken-Hui Chen ,  Chin-Hung Chang

    IPC: G06F12/06

    Abstract: A nested wrap-around technology includes an address counter and associated logic for generating addresses to perform a nested wrap-around access operation. The nested wrap-around access operation may be a read or a write operation. A wrap-around section length and a wrap-around count define a wrap-around block. A wrap starting address, initially set to a supplied start address, is offset from a lower boundary of a wrap-around section. Access starts at a wrap starting address and proceeds in a wrap-around manner within a wrap-around section. After access of the address immediately preceding the wrap starting address, the wrap starting address is incremented by the wrap-around section length, or, if the wrap-around section is the last one in the wrap-around block, the wrap starting address is set to the lower boundary of the wrap-around block plus the offset. Access continues until a termination event.

    ECC method for flash memory
    22.
    发明授权
    ECC method for flash memory 有权
    闪存的ECC方法

    公开(公告)号：US09535785B2

    公开(公告)日：2017-01-03

    申请号：US14158613

    申请日：2014-01-17

    Applicant: Macronix International Co., Ltd.

    Inventor： Nai-Ping Kuo ,  Shih-Chang Huang ,  Chin-Hung Chang ,  Ken-Hui Chen ,  Kuen-Long Chang ,  Chun-Hsiung Hung

    IPC: G06F11/10 ,  G11C16/34

    CPC classification number: G06F11/1048 ,  G06F2212/1036 ,  G11C16/3436

    Abstract: A method of operating a memory storing data sets, and ECCs for the data sets is provided. The method includes when writing new data in a data set, computing and storing an ECC, if a number of addressable segments storing the new data and data previously programmed in the data set includes at least a predetermined number of addressable segments. The method includes storing indications for whether to enable or disable use of the ECCs, using the ECC and a first additional ECC bit derived from the ECC. The method includes reading from a data set an extended ECC including an ECC and a first additional ECC bit derived from the ECC, and enabling or disabling use of the ECC according to the indications stored for the data set. The method includes enabling use of ECCs for blank data sets, using the indications and a second additional ECC bit.

    Abstract translation: 提供了一种操作存储数据集的存储器和数据集的ECC的方法。 如果存储新数据的多个可寻址段和先前在数据集中编程的数据包括至少预定数量的可寻址段，则该方法包括在将新数据写入数据集时，计算和存储ECC。 该方法包括使用ECC和从ECC导出的第一附加ECC比特来存储是否启用或禁止使用ECC的指示。 该方法包括从数据集读取包括ECC的扩展ECC和从ECC导出的第一附加ECC位，以及根据为数据集存储的指示启用或禁用ECC的使用。 该方法包括使用所述指示和第二附加ECC位使能ECC空白数据集。

    INPUT PIN CONTROL
    23.
    发明申请
    INPUT PIN CONTROL 有权
    输入PIN控制

    公开(公告)号：US20150323946A1

    公开(公告)日：2015-11-12

    申请号：US14274237

    申请日：2014-05-09

    Applicant: Macronix International Co., Ltd.

    Inventor： Kuen-Long Chang ,  Ken-Hui Chen ,  Chin-Hung Chang ,  Chao-Hsin Lin

    IPC: G05F1/46

    CPC classification number: G05F1/46 ,  G05F1/468 ,  H03K17/22

    Abstract: An integrated circuit device includes a pad adapted to receive a signal from an external driver. A state register is programmed with a state that indicates a voltage level to set for the pad during initialization of circuitry on the integrated circuit device responsive to the state for the pad. The voltage level may correspond to a logic low level or a logic high level. A voltage holding circuit is coupled to the pad and the state register, and is configured to force the pad to the voltage level in response to an event that causes the initialization.

    Abstract translation: 集成电路器件包括适于从外部驱动器接收信号的焊盘。 状态寄存器被编程为响应于该焊盘的状态而指示在集成电路器件的电路初始化期间为焊盘设置的电压电平的状态。 电压电平可以对应于逻辑低电平或逻辑高电平。 电压保持电路耦合到焊盘和状态寄存器，并且被配置为响应于引起初始化的事件而迫使焊盘达到电压电平。

    ECC METHOD FOR FLASH MEMORY
    25.
    发明申请
    ECC METHOD FOR FLASH MEMORY 有权
    闪存存储器的ECC方法

    公开(公告)号：US20150205665A1

    公开(公告)日：2015-07-23

    申请号：US14158613

    申请日：2014-01-17

    Applicant: Macronix International Co., Ltd.

    Inventor： Nai-Ping Kuo ,  Shih-Chang Huang ,  Chin-Hung Chang ,  Ken-Hui Chen ,  Kuen-Long Chang ,  Chun-Hsiung Hung

    IPC: G06F11/10

    CPC classification number: G06F11/1048 ,  G06F2212/1036 ,  G11C16/3436

    Abstract: A method of operating a memory storing data sets, and ECCs for the data sets is provided. The method includes when writing new data in a data set, computing and storing an ECC, if a number of addressable segments storing the new data and data previously programmed in the data set includes at least a predetermined number of addressable segments. The method includes storing indications for whether to enable or disable use of the ECCs, using the ECC and a first additional ECC bit derived from the ECC. The method includes reading from a data set an extended ECC including an ECC and a first additional ECC bit derived from the ECC, and enabling or disabling use of the ECC according to the indications stored for the data set. The method includes enabling use of ECCs for blank data sets, using the indications and a second additional ECC bit.

    Abstract translation: 提供了一种操作存储数据集的存储器和数据集的ECC的方法。 如果存储新数据的多个可寻址段和先前在数据集中编程的数据包括至少预定数量的可寻址段，则该方法包括在将新数据写入数据集时，计算和存储ECC。 该方法包括使用ECC和从ECC导出的第一附加ECC比特来存储是否启用或禁止使用ECC的指示。 该方法包括从数据集读取包括ECC的扩展ECC和从ECC导出的第一附加ECC位，以及根据为数据集存储的指示启用或禁用ECC的使用。 该方法包括使用所述指示和第二附加ECC位使能ECC空白数据集。

    Memory device and associated control method
    27.
    发明授权
    Memory device and associated control method 有权

    公开(公告)号：US12197745B2

    公开(公告)日：2025-01-14

    申请号：US17817711

    申请日：2022-08-05

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Chin-Hung Chang ,  Chia-Jung Chen ,  Ken-Hui Chen ,  Chun-Hsiung Hung

    IPC: G06F3/06

    Abstract: A memory device and an associated control method are provided. The memory device includes a non-volatile memory array and a memory control circuit. The non-volatile memory array includes M secured memory zones. The memory control circuit is electrically connected to the non-volatile memory array. The memory control circuit provides a set of mapping information and searches a request key in the set of mapping information. The set of mapping information represents correspondences between N access keys and the M secured memory zones. The memory control circuit acquires at least one of the M secured memory zones if the request key is one of the N access keys, and performs an access command to the at least one of the M secured memory zones. M and N are positive integers.

    Configurable security memory region
    29.
    发明授权
    Configurable security memory region 有权

    公开(公告)号：US10809925B2

    公开(公告)日：2020-10-20

    申请号：US16259268

    申请日：2019-01-28

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Ken-Hui Chen ,  Kuen-Long Chang ,  Chin-Hung Chang ,  Yu-Chen Wang

    IPC: G06F3/06 ,  G06F12/14

    Abstract: A memory device comprises a memory array with I/O path and security circuitry coupled to the I/O path of the memory array. The memory device comprises control circuitry, responsive to configuration data, to invoke the security circuitry. The memory device comprises a configuration store, storing the configuration data accessible by the control circuitry to specify location and size of a security memory region in the memory array. Responsive to an external command and the configuration data, the control circuitry can be configured to invoke the security circuitry on an operation specified in the external command in response to accesses into the security memory region, or to not invoke the security circuitry in response to accesses to outside the security memory region.

    Multi-chip package, controlling method of multi-chip package and security chip
    30.
    发明申请
    Multi-chip package, controlling method of multi-chip package and security chip 审中-公开

    公开(公告)号：US20200057575A1

    公开(公告)日：2020-02-20

    申请号：US15998456

    申请日：2018-08-15

    Applicant: Macronix International Co., Ltd.

    Inventor： Chia-Jung Chen ,  Chin-Hung Chang ,  Ken-Hui Chen

    IPC: G06F3/06

    Abstract: A multi-chip package, a controlling method of the multi-chip package and a security chip are provided. The multi-chip package includes a memory chip and a security chip. The security chip is coupled between the memory chip and a host. The security chip includes a processing circuit. The processing circuit is for enabling a security path to input an input-output signal into the processing circuit for executing a security procedure and accessing the memory chip, if a command is received by the processing circuit and the command includes a security requirement.

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