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    MANAGING TAMPER DETECTIONS IN SECURE MEMORY DEVICES
    1.
    发明申请
    MANAGING TAMPER DETECTIONS IN SECURE MEMORY DEVICES 有权

    公开(公告)号：US20210342065A1

    公开(公告)日：2021-11-04

    申请号：US16862129

    申请日：2020-04-29

    Applicant: Macronix International Co., Ltd.

    Inventor： Chin-Hung Chang ,  Chia-Feng Cheng

    IPC: G06F3/06

    Abstract: Systems, methods, circuits, devices, and apparatus including computer-readable mediums for managing tamper detections in secure memory devices. In one aspect, a secure memory device includes: a memory cell array, one or more tamper detectors each configured to detect a respective type of tamper event on at least part of the secure memory device, and a tamper detection status register storing one or more values each indicating a tamper detection status detected by a corresponding tamper detector. The secure memory device can include a command interface coupled to the tamper detection status register and configured to output the values stored in the tamper detection status register when receiving a trigger. The secure memory device can also include an output pin coupled to the tamper detection status register and be configured to automatically output the values stored in the tamper detection status register via the output pin.

    Data recovery method to error correction code in memory
    2.
    发明授权
    Data recovery method to error correction code in memory 有权

    公开(公告)号：US10725862B2

    公开(公告)日：2020-07-28

    申请号：US16029344

    申请日：2018-07-06

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Chia-Feng Cheng ,  Chun-Hsiung Hung

    IPC: G06F11/10 ,  G06F3/06 ,  G11C29/52

    Abstract: An integrated circuit comprising a memory array configured to store data chunks with corresponding error correction codes and error correction logic includes control logic that executes a recovery procedure to access a selected data chunk and corresponding error correction code from the memory array, to utilize the error correction logic to identify a location in the memory array of an error bit in the selected data chunk, and to access the identified location to write the corrected data. The recovery procedure is sequentially applied to a plurality of data chunks over a recovery operation region designated for a given instance of the recovery operation. Memory coupled with the control logic can store one or more recovery parameters that identify the recovery operation region in the memory.

    METHOD AND APPARATUS FOR LEAKAGE SUPPRESSION IN FLASH MEMORY IN RESPONSE TO EXTERNAL COMMANDS
    3.
    发明申请
    METHOD AND APPARATUS FOR LEAKAGE SUPPRESSION IN FLASH MEMORY IN RESPONSE TO EXTERNAL COMMANDS 有权
    FLASH存储器中对外部命令的泄漏抑制方法和装置

    公开(公告)号：US20140219026A1

    公开(公告)日：2014-08-07

    申请号：US14249270

    申请日：2014-04-09

    Applicant: Macronix International Co., Ltd.

    Inventor： Nai-Ping Kuo ,  Su-Chueh Lo ,  Kuen-Long Chang ,  Chun-Hsiung Hung ,  Chia-Feng Cheng ,  Ken-Hui Chen ,  Yu-Chen Wang

    IPC: G11C16/34

    CPC classification number: G11C16/3409 ,  G11C11/5635 ,  G11C16/0483 ,  G11C16/14

    Abstract: Techniques are described herein for detecting and recovering over-erased memory cells in a flash memory device. In one embodiment, a flash memory device includes a memory array including a plurality of blocks of memory cells. The device also includes a command interface to receive a command from a source external to the memory device. The device also includes a controller including logic to perform a leakage-suppression process in response to the command. The leakage-suppression process includes performing a soft program operation to increase a threshold voltage of one or more over-erased memory cells in a given block of memory cells and establish an erased state.

    Abstract translation: 本文描述了用于检测和恢复闪存设备中的过擦除存储器单元的技术。 在一个实施例中，闪存器件包括包括多个存储单元块的存储器阵列。 该设备还包括用于从存储设备外部的源接收命令的命令接口。 该装置还包括控制器，其包括响应于该命令执行泄漏抑制处理的逻辑。 泄漏抑制处理包括执行软程序操作以增加给定的存储单元块中的一个或多个过擦除存储器单元的阈值电压并建立擦除状态。

    Method and apparatus for leakage suppression in flash memory in response to external commands
    4.
    发明授权
    Method and apparatus for leakage suppression in flash memory in response to external commands 有权
    响应于外部命令，闪存中泄漏抑制的方法和装置

    公开(公告)号：US09093172B2

    公开(公告)日：2015-07-28

    申请号：US14249270

    申请日：2014-04-09

    Applicant: Macronix International Co., Ltd.

    Inventor： Nai-Ping Kuo ,  Su-Chueh Lo ,  Kuen-Long Chang ,  Chun-Hsiung Hung ,  Chia-Feng Cheng ,  Ken-Hui Chen ,  Yu-Chen Wang

    IPC: G11C11/34 ,  G11C16/34 ,  G11C11/56 ,  G11C16/04 ,  G11C16/14

    CPC classification number: G11C16/3409 ,  G11C11/5635 ,  G11C16/0483 ,  G11C16/14

    Abstract: Techniques are described herein for detecting and recovering over-erased memory cells in a flash memory device. In one embodiment, a flash memory device includes a memory array including a plurality of blocks of memory cells. The device also includes a command interface to receive a command from a source external to the memory device. The device also includes a controller including logic to perform a leakage-suppression process in response to the command. The leakage-suppression process includes performing a soft program operation to increase a threshold voltage of one or more over-erased memory cells in a given block of memory cells and establish an erased state.

    Abstract translation: 本文描述了用于检测和恢复闪存设备中的过擦除存储器单元的技术。 在一个实施例中，闪存器件包括包括多个存储单元块的存储器阵列。 该设备还包括用于从存储设备外部的源接收命令的命令接口。 该装置还包括控制器，其包括响应于该命令执行泄漏抑制处理的逻辑。 泄漏抑制处理包括执行软程序操作以增加给定的存储单元块中的一个或多个过擦除存储器单元的阈值电压并建立擦除状态。

    Monitoring data error status in a memory
    9.
    发明授权
    Monitoring data error status in a memory 有权
    监视存储器中的数据错误状态

    公开(公告)号：US09519539B2

    公开(公告)日：2016-12-13

    申请号：US14612369

    申请日：2015-02-03

    Applicant: Macronix International Co., Ltd.

    Inventor： Kuen Long Chang ,  Ken Hui Chen ,  Su Chueh Lo ,  Chia-Feng Cheng

    IPC: G11C29/00 ,  G06F11/10 ,  G06F3/06

    CPC classification number: G06F11/1004 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0653

    Abstract: A method for outputting data error status of a memory device includes generating data status indication codes indicating error status of data chunks transmitted by a memory controller, and combining the data status indication codes with corresponding data chunks to generate an output signal, and outputting the output signal to a data bus pin.

    Abstract translation: 一种用于输出存储器件的数据错误状态的方法，包括产生指示由存储器控制器发送的数据块的错误状态的数据状态指示代码，并将数据状态指示代码与相应的数据块组合以产生输出信号，并输出输出 信号到数据总线引脚。

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