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    FLASH MEMORY AND WRITING METHOD THEREOF
    2.
    发明申请
    FLASH MEMORY AND WRITING METHOD THEREOF 有权

    公开(公告)号：US20220283738A1

    公开(公告)日：2022-09-08

    申请号：US17192807

    申请日：2021-03-04

    Applicant: MACRONIX International Co., Ltd.

    Inventor： Chun-Lien Su ,  Chang-Ting Chen

    IPC: G06F3/06 ,  G06F12/06 ,  G11C16/04 ,  G11C16/10 ,  G11C16/14

    Abstract: A flash memory and a writing method thereof are provided. The flash memory includes a plurality of memory blocks and a plurality of multiplex circuits. The memory blocks are arranged into a plurality of memory banks. Each of the memory blocks transmits a plurality of erase voltages or a plurality of program voltages to the corresponding memory bank for executing an erase operation or a program operation. The program operation is executed by one of the memory banks while the erase operation is executed by another one of the memory banks according to a programming while erasing instruction.

    Devices and operation methods for configuring data strobe signal in memory device
    3.
    发明授权
    Devices and operation methods for configuring data strobe signal in memory device 有权

    公开(公告)号：US09652228B2

    公开(公告)日：2017-05-16

    申请号：US14677321

    申请日：2015-04-02

    Applicant: Macronix International Co., Ltd.

    Inventor： Kuen-Long Chang ,  Ken-Hui Chen ,  Chang-Ting Chen

    IPC: G06F12/00 ,  G06F9/00

    CPC classification number: G06F9/00 ,  G06F1/12 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C16/00 ,  G11C29/023

    Abstract: A non-volatile memory device includes a memory core storing data to be output from the memory core according to an external clock signal, an input buffer receiving the external clock signal and providing an input clock signal, and a synchronization circuit including a delay circuit and configured to receive the input clock signal, provide an output clock signal, and synchronize the output clock signal to the external clock signal. The device further includes a data strobe output buffer receiving the output clock signal and providing a data strobe signal having a signal delay configurable relative to the external clock signal, a clocked circuit element receiving the data and the output clock signal and outputting the data in synchronism with the output clock signal, and a delay control circuit providing a delay control signal to the delay circuit to modify the signal delay of the data strobe signal.

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