公开(公告)号：US08073986B2

公开(公告)日：2011-12-06

申请号：US12782232

申请日：2010-05-18

Applicant: Petro Estakhri ,  Mahmud Assar

Inventor： Petro Estakhri ,  Mahmud Assar

IPC: G06F3/00

CPC classification number: G11C7/1045 ,  G06F13/4081 ,  G11C7/20

Abstract: Memory devices having a memory module, an interface, identification circuitry and a controller coupled to the memory module and the identification circuitry. The identification circuitry is configured to identify a selected operating mode from a plurality of signals sensed at the interface in response to a plurality of signals previously applied to the interface by the identification circuitry. The controller is operable to configure the memory device to the selected operating mode responsive to the identification circuitry.

Abstract translation: 具有存储器模块，接口，识别电路和耦合到存储器模块和识别电路的控制器的存储器件。 识别电路被配置为响应于先前通过识别电路施加到接口的多个信号，从在接口处感测到的多个信号中识别所选择的操作模式。 控制器可操作以响应于识别电路将存储器件配置为所选择的操作模式。

公开(公告)号：US20100228890A1

公开(公告)日：2010-09-09

申请号：US12782232

申请日：2010-05-18

Applicant: Petro Estakhri ,  Mahmud Assar

Inventor： Petro Estakhri ,  Mahmud Assar

IPC: G06F3/00 ,  G06F12/02

CPC classification number: G11C7/1045 ,  G06F13/4081 ,  G11C7/20

Abstract: Memory devices having a memory module, an interface, identification circuitry and a controller coupled to the memory module and the identification circuitry. The identification circuitry is configured to identify a selected operating mode from a plurality of signals sensed at the interface in response to a plurality of signals previously applied to the interface by the identification circuitry. The controller is operable to configure the memory device to the selected operating mode responsive to the identification circuitry.

Abstract translation: 具有存储器模块，接口，识别电路和耦合到存储器模块和识别电路的控制器的存储器件。 识别电路被配置为响应于先前通过识别电路施加到接口的多个信号，从在接口处感测到的多个信号中识别所选择的操作模式。 控制器可操作以响应于识别电路将存储器件配置为所选择的操作模式。

公开(公告)号：US20090204750A1

公开(公告)日：2009-08-13

申请号：US12426662

申请日：2009-04-20

Applicant: Petro Estakhri ,  Mahmud Assar

Inventor： Petro Estakhri ,  Mahmud Assar

IPC: G06F12/00 ,  G06F12/10 ,  G06F12/02

CPC classification number: G11C29/765 ,  G06F3/0613 ,  G06F3/0616 ,  G06F3/064 ,  G06F3/0679 ,  G06F11/1068 ,  G06F12/023 ,  G06F12/0246 ,  G11C16/08 ,  G11C16/102 ,  G11C29/82

Abstract: A nonvolatile semiconductor mass storage system and architecture can be substituted for a rotating hard disk. The system and architecture avoid an erase cycle each time information stored in the mass storage is changed. Erase cycles are avoided by programming an altered data file into an empty mass storage block rather than over itself as a hard disk would. Periodically, the mass storage will need to be cleaned up. These advantages are achieved through the use of several flags, and a map to correlate a logical block address of a block to a physical address of that block. In particular, flags are provided for defective blocks, used blocks, and old versions of a block. An array of volatile memory is addressable according to the logical address and stores the physical address.

Abstract translation: 非易失性半导体大容量存储系统和架构可以代替旋转硬盘。 每当存储在大容量存储器中的信息改变时，系统和架构避免了擦除周期。 通过将更改的数据文件编程为空的大容量存储块而不是以硬盘为单位，可以避免擦除周期。 定期地，大容量存储将需要清理。 这些优点通过使用多个标志来实现，以及将块的逻辑块地址与该块的物理地址相关联的映射。 特别地，为缺陷块，使用的块和块的旧版本提供标志。 易失性存储器阵列根据逻辑地址可寻址，并存储物理地址。

公开(公告)号：US06912618B2

公开(公告)日：2005-06-28

申请号：US09850790

申请日：2001-05-07

Applicant: Petro Estakhri ,  Mahmud Assar

Inventor： Petro Estakhri ,  Mahmud Assar

IPC: G06F3/06 ,  G06F11/10 ,  G06F12/02 ,  G11C16/08 ,  G11C16/10 ,  G11C29/00 ,  G06F12/00

CPC classification number: G11C29/765 ,  G06F3/0613 ,  G06F3/0616 ,  G06F3/064 ,  G06F3/0679 ,  G06F11/1068 ,  G06F12/023 ,  G06F12/0246 ,  G11C16/08 ,  G11C16/102 ,  G11C29/82

Abstract: A nonvolatile semiconductor mass storage system and architecture can be substituted for a rotating hard disk. The system and architecture avoid an erase cycle each time information stored in the mass storage is changed. Erase cycles are avoided by programming an altered data file into an empty mass storage block rather than over itself as a hard disk would. Periodically, the mass storage will need to be cleaned up. These advantages are achieved through the use of several flags, and a map to correlate a logical block address of a block to a physical address of that block. In particular, flags are provided for defective blocks, used blocks, and old versions of a block. An array of volatile memory is addressable according to the logical address and stores the physical address.

Abstract translation: 非易失性半导体大容量存储系统和架构可以代替旋转硬盘。 每当存储在大容量存储器中的信息改变时，系统和架构避免了擦除周期。 通过将更改的数据文件编程为空的大容量存储块而不是以硬盘为单位，可以避免擦除周期。 定期地，大容量存储将需要清理。 这些优点通过使用多个标志来实现，以及将块的逻辑块地址与该块的物理地址相关联的映射。 特别地，为缺陷块，使用的块和块的旧版本提供标志。 易失性存储器阵列根据逻辑地址可寻址，并存储物理地址。

公开(公告)号：US06182162B2

公开(公告)日：2001-01-30

申请号：US09034173

申请日：1998-03-02

Applicant: Petro Estakhri ,  Mahmud Assar

Inventor： Petro Estakhri ,  Mahmud Assar

IPC: G06F1300

CPC classification number: G11C7/1045 ,  G06F13/4081 ,  G11C7/20

Abstract: An improved compact flash memory card system includes an improved compact flash memory card desktop adapter and an improved compact flash memory card. The improved compact flash memory card desktop adapter utilizes a fifty pin socket to interface with the compact flash memory card. The desktop adapter also utilizes a plug adapter to interface with a computer. For more efficient communication between the improved compact flash memory card and the computer, the improved desktop adapter adopts the universal serial bus architecture. The improved compact flash memory card utilizes a fifty pin connection to interface with a computer through an interface device. The fifty pin connection of the flash memory card can be used with different interface devices in a variety of configurations such as a universal serial bus mode, PCMCIA mode, and ATA IDE mode. Each of these modes of operation require different protocols. Upon initialization with an interface device, this improved compact flash memory card automatically detects which operation mode is used by this interface device and configures the memory card to be compatible with the present operation mode. Because all fifty pins of the flash memory card are occupied to either transfer data or provide control signals to and from the flash memory card, this improved flash memory card merely senses selected pins to determine the present mode of operation.

Abstract translation: 改进的紧凑型闪存卡系统包括改进的紧凑型闪存卡桌面适配器和改进的紧凑型闪存卡。 改进的紧凑型闪存卡桌面适配器使用五十针插座与紧凑型闪存卡进行接口。 桌面适配器还使用插头适配器与计算机进行接口。 改进的紧凑型闪存卡和计算机之间的通信更为有效，改进的桌面适配器采用通用串行总线架构。 改进的紧凑型闪存卡利用五十针连接通过接口设备与计算机接口。 闪存卡的五十针连接可以在各种配置中使用，例如通用串行总线模式，PCMCIA模式和ATA IDE模式。 这些操作模式中的每一种都需要不同的协议。 在使用接口设备初始化时，该改进的紧凑型闪存卡自动检测该接口设备使用哪种操作模式，并将存储卡配置为与当前操作模式兼容。 因为闪存卡的所有五十个引脚都被占用以传输数据或向闪存卡提供控制信号，所以该改进的闪存卡仅仅感测所选择的引脚以确定当前的操作模式。

公开(公告)号：US5479638A

公开(公告)日：1995-12-26

申请号：US37893

申请日：1993-03-26

Applicant: Mahmud Assar ,  Siamack Nemazie ,  Petro Estakhri

Inventor： Mahmud Assar ,  Siamack Nemazie ,  Petro Estakhri

IPC: G06F3/06 ,  G06F12/02 ,  G06F12/14

CPC classification number: G06F3/0601 ,  G06F12/0246 ,  G06F12/0292 ,  G06F2003/0694 ,  G06F2212/1036 ,  G06F2212/7211 ,  Y10S706/90

Abstract: A semiconductor mass storage device can be substituted for a rotating hard disk. The device avoids an erase cycle each time information stored in the mass storage is changed. (The erase cycle is understood to include, fully programming the block to be erased, and then erasing the block.) Erase cycles are avoided by programming an altered data file into an empty mass storage block rather than over itself as a hard disk would. Periodically, the mass storage will need to be cleaned up. Secondly, a circuit for evenly using all blocks in the mass storage is provided. These advantages are achieved through the use of several flags, a map to directly correlate a logical address of a block to a physical address of that block and a count register for each block. In particular, flags are provided for defective blocks, used blocks, old version of a block, a count to determine the number of times a block has been erased and written and erase inhibit.

Abstract translation: 半导体大容量存储装置可以代替旋转硬盘。 每当存储在大容量存储器中的信息改变时，该装置避免擦除循环。 （擦除周期被理解为包括完全编程要擦除的块，然后擦除块）。通过将更改的数据文件编程为空的大容量存储块而不是将其自身作为硬盘来避免擦除周期。 定期地，大容量存储将需要清理。 其次，提供了用于均匀地使用大容量存储器中的所有块的电路。 这些优点通过使用几个标志来实现，地图将块的逻辑地址与该块的物理地址和每个块的计数寄存器直接相关。 特别地，为缺陷块，使用块，旧版块提供标志，确定块被擦除和写入和擦除禁止的次数的计数。

公开(公告)号：US08032694B2

公开(公告)日：2011-10-04

申请号：US12844354

申请日：2010-07-27

Applicant: Petro Estakhri ,  Mahmud Assar

Inventor： Petro Estakhri ,  Mahmud Assar

IPC: G06F13/00 ,  G06F13/28 ,  G06F9/26 ,  G06F9/34

CPC classification number: G11C29/765 ,  G06F3/0613 ,  G06F3/0616 ,  G06F3/064 ,  G06F3/0679 ,  G06F11/1068 ,  G06F12/023 ,  G06F12/0246 ,  G11C16/08 ,  G11C16/102 ,  G11C29/82

Abstract: A nonvolatile semiconductor mass storage system and architecture can be substituted for a rotating hard disk. The system and architecture avoid an erase cycle each time information stored in the mass storage is changed. Erase cycles are avoided by programming an altered data file into an empty mass storage block rather than over itself as a hard disk would. Periodically, the mass storage will need to be cleaned up. These advantages are achieved through the use of several flags, and a map to correlate a logical block address of a block to a physical address of that block. In particular, flags are provided for defective blocks, used blocks, and old versions of a block. An array of volatile memory is addressable according to the logical address and stores the physical address.

Abstract translation: 非易失性半导体大容量存储系统和架构可以代替旋转硬盘。 每当存储在大容量存储器中的信息改变时，系统和架构避免了擦除周期。 通过将更改的数据文件编程为空的大容量存储块而不是以硬盘为单位，可以避免擦除周期。 定期地，大容量存储将需要清理。 这些优点通过使用多个标志来实现，以及将块的逻辑块地址与该块的物理地址相关联的映射。 特别地，为缺陷块，使用的块和块的旧版本提供标志。 易失性存储器阵列根据逻辑地址可寻址，并存储物理地址。

公开(公告)号：US07111085B2

公开(公告)日：2006-09-19

申请号：US10647084

申请日：2003-08-21

Applicant: Petro Estakhri ,  Mahmud Assar

Inventor： Petro Estakhri ,  Mahmud Assar

IPC: G06F3/00

CPC classification number: G11C7/20 ,  G06F13/387 ,  G06F13/4081 ,  G06F2213/0042 ,  G11C7/1045

Abstract: An interfacing system facilitating user-friendly connectivity in a selected operating mode between a host computer system and a flash memory card. The interfacing system includes an interface device and a flash memory card. The interfacing system features significantly expanded operating mode detection capability within the flash memory card and marked reduction in the incorrect detection of the operating mode. The interface device includes a first end for coupling to the host computer and a second end for coupling to the flash memory card, while supporting communication in the selected operating mode which is also supported by the host computer system. The flash memory card utilizes a fifty pin connection to interface with the host computer system through the interface device. The fifty pin connection of the flash memory card can be used with different interface devices in a variety of configurations such as a universal serial mode, PCMCIA mode, and ATA IDE mode. Each of these modes of operation require different protocols.

公开(公告)号：US06385667B1

公开(公告)日：2002-05-07

申请号：US09234430

申请日：1999-01-20

Applicant: Petro Estakhri ,  Mahmud Assar

Inventor： Petro Estakhri ,  Mahmud Assar

IPC: G06F1314

CPC classification number: G11C7/1045 ,  G06F13/4081 ,  G11C7/20

Abstract: An interfacing system facilitating user-friendly connectivity in a selected operating mode between a host computer system and a flash memory card. The interfacing system includes an interface device and a flash memory card. The interfacing system features significantly expanded operating mode detection capability within the flash memory card and marked reduction in the incorrect detection of the operating mode. The interface device includes a first end for coupling to the host computer and a second end for coupling to the flash memory card, while supporting communication in the selected operating mode which is also supported by the host computer system. The flash memory card utilizes a fifty pin connection to interface with the host computer system through the interface device. The fifty pin connection of the flash memory card can be used with different interface devices in a variety of configurations such as a universal serial mode, PCMCIA mode, and ATA IDE mode. Each of these modes of operation require different protocols. Upon initialization with the interface device, the flash memory card automatically detects the selected operating mode of the interface device and configures itself to operate with the selected operating mode. The operating mode detection is accomplished by sensing unencoded signals and encoded signals. The encoded signals are encoded with a finite set of predetermined codes. Each predetermined code uniquely identifies a particular operating mode.

Abstract translation: 一种接口系统，在主计算机系统和闪存卡之间以选定的操作模式促进用户友好的连接。 接口系统包括接口设备和闪存卡。 接口系统具有显着扩展闪存卡内的工作模式检测功能，并显着减少了操作模式的错误检测。 接口设备包括用于耦合到主计算机的第一端和用于耦合到闪存卡的第二端，同时支持主机计算机系统也支持的所选操作模式中的通信。 闪存卡利用五十针连接通过接口设备与主机系统进行接口。 闪存卡的五十针连接可以在各种配置中使用，例如通用串行模式，PCMCIA模式和ATA IDE模式。 这些操作模式中的每一种都需要不同的协议。 在使用接口设备进行初始化时，闪存卡会自动检测接口设备的选定操作模式，并配置自身以所选择的操作模式进行操作。 通过感测未编码的信号和编码信号来实现操作模式检测。 编码信号用有限的一组预定码进行编码。 每个预定代码唯一地标识特定的操作模式。

公开(公告)号：US5157618A

公开(公告)日：1992-10-20

申请号：US486337

申请日：1990-02-28

Applicant: H. Ravindra ,  Suhas S. Patil ,  Ernest S. Lin ,  Mahmud Assar ,  Dayakar Reddy

Inventor： H. Ravindra ,  Suhas S. Patil ,  Ernest S. Lin ,  Mahmud Assar ,  Dayakar Reddy

IPC: H03K19/173 ,  H03K19/177

CPC classification number: H03K19/1735 ,  H03K19/1736 ,  H03K19/17712

Abstract: Disclosed is a set of functional components (tiles), consisting in part of subgate elements, which, by their design, facilitate the creation of dense integrated circuits, without forfeiting the capability of modifying the functionality of individual tiles by late mask programming techniques. Overall densities approaching those obtained with hand-crafted, custom designs can be obtained in part because such components are designed to be tiled throughout a storage logic array, permitting the creation of orthogonal logic gates as well as individual gates (and more complex functions) the functionality of which is distributed horizontally, vertically and even in a zigzag fashion. Moreover, the transition time from prototype to high volume manufacturing is reduced significantly due to the ease with which even complex functions can be repaired and enhanced.

Abstract translation: 公开了一组由部分子门元件构成的功能部件（瓦片），其通过其设计有助于创建密集的集成电路，而不会通过后期掩模编程技术来丧失修改各个瓦片的功能的能力。 通过手工制作的定制设计获得的总体密度可以部分地被获得，这是因为这样的部件设计成在整个存储逻辑阵列中被平铺，允许创建正交逻辑门以及单独的门（和更复杂的功能） 其功能水平，垂直分布，甚至以锯齿形的方式分布。 此外，由于易于修复和增强复杂功能，从原型到大批量制造的转换时间显着减少。