公开(公告)号：US08293609B2

公开(公告)日：2012-10-23

申请号：US13355221

申请日：2012-01-20

Applicant: Rohit Pal ,  Frank Bin Yang ,  Michael J. Hargrove

Inventor： Rohit Pal ,  Frank Bin Yang ,  Michael J. Hargrove

IPC: H01L21/336

CPC classification number: H01L29/66636 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/3065 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/7848

Abstract: Semiconductor transistor devices and related fabrication methods are provided. An exemplary transistor device includes a layer of semiconductor material having a channel region defined therein and a gate structure overlying the channel region. Recesses are formed in the layer of semiconductor material adjacent to the channel region, such that the recesses extend asymmetrically toward the channel region. The transistor device also includes stress-inducing semiconductor material formed in the recesses. The asymmetric profile of the stress-inducing semiconductor material enhances carrier mobility in a manner that does not exacerbate the short channel effect.

Abstract translation: 提供半导体晶体管器件及相关制造方法。 示例性晶体管器件包括其中限定有沟道区的半导体材料层和覆盖沟道区的栅极结构。 凹槽在与沟道区相邻的半导体材料层中形成，使得凹槽朝向沟道区不对称地延伸。 晶体管器件还包括形成在凹槽中的应力诱导半导体材料。 应力诱导半导体材料的不对称轮廓以不会加剧短通道效应的方式提高载流子迁移率。

公开(公告)号：US08278165B2

公开(公告)日：2012-10-02

申请号：US12577628

申请日：2009-10-12

Applicant: Rohit Pal ,  Janice Monzet

Inventor： Rohit Pal ,  Janice Monzet

IPC: H01L21/8238

CPC classification number: H01L21/823807 ,  H01L21/31111 ,  H01L21/823878

Abstract: Methods for fabricating semiconductor devices are provided. The methods include providing a semiconductor substrate having pFET and nFET regions, each having active areas and shallow trench isolation. A hardmask layer is formed overlying the semiconductor substrate. A photoresist layer is provided over the hardmask layer. The phoresist layer is patterned. An exposed portion of the hardmask layer is removed from one of the pFET region and nFET region with the patterned photoresist acting as an etch mask to define a masked region and an unmasked region. An epitaxial silicon layer is formed on the active area in the unmasked region. A protective oxide layer is formed overlying the epitaxial silicon layer. The hardmask layer is removed from the masked region with the protective oxide layer protecting the epitaxial silicon layer during such removal step. The protective oxide layer is removed from the epitaxial silicon layer.

Abstract translation: 提供制造半导体器件的方法。 所述方法包括提供具有pFET和nFET区域的半导体衬底，每个具有有源区和浅沟槽隔离。 形成覆盖半导体衬底的硬掩模层。 在硬掩模层上提供光致抗蚀剂层。 光刻胶层被图案化。 硬掩模层的暴露部分从pFET区域和nFET区域中的一个去除，图案化的光致抗蚀剂用作蚀刻掩模以限定掩蔽区域和未掩模区域。 在未掩模区域的有源区域上形成外延硅层。 形成覆盖在外延硅层上的保护性氧化物层。 在这种去除步骤期间，保护氧化层保护外延硅层，从屏蔽区域去除硬掩模层。 从外延硅层去除保护氧化物层。

公开(公告)号：US08148750B2

公开(公告)日：2012-04-03

申请号：US13052969

申请日：2011-03-21

Applicant: Rohit Pal ,  Frank Bin Yang ,  Michael J. Hargrove

Inventor： Rohit Pal ,  Frank Bin Yang ,  Michael J. Hargrove

IPC: H01L21/02

CPC classification number: H01L29/66636 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/3065 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/7848

Abstract: Semiconductor transistor devices and related fabrication methods are provided. An exemplary transistor device includes a layer of semiconductor material having a channel region defined therein and a gate structure overlying the channel region. Recesses are formed in the layer of semiconductor material adjacent to the channel region, such that the recesses extend asymmetrically toward the channel region. The transistor device also includes stress-inducing semiconductor material formed in the recesses. The asymmetric profile of the stress-inducing semiconductor material enhances carrier mobility in a manner that does not exacerbate the short channel effect.

Abstract translation: 提供半导体晶体管器件及相关制造方法。 示例性晶体管器件包括其中限定有沟道区的半导体材料层和覆盖沟道区的栅极结构。 凹槽在与沟道区相邻的半导体材料层中形成，使得凹槽朝向沟道区不对称地延伸。 晶体管器件还包括形成在凹槽中的应力诱导半导体材料。 应力诱导半导体材料的不对称轮廓以不会加剧短通道效应的方式提高载流子迁移率。

公开(公告)号：US20110298008A1

公开(公告)日：2011-12-08

申请号：US12795683

申请日：2010-06-08

Applicant: Brian J. Greene ,  William K. Henson ,  Judson R. Holt ,  Michael D. Steigerwalt ,  Kuldeep Amarnath ,  Rohit Pal ,  Johan W. Weijtmans

Inventor： Brian J. Greene ,  William K. Henson ,  Judson R. Holt ,  Michael D. Steigerwalt ,  Kuldeep Amarnath ,  Rohit Pal ,  Johan W. Weijtmans

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/66636 ,  H01L21/3247 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/7848

Abstract: A low energy surface is formed by a high temperature anneal of the surfaces of trenches on each side of a gate stack. The material of the semiconductor layer reflows during the high temperature anneal such that the low energy surface is a crystallographic surface that is at a non-orthogonal angle with the surface normal of the semiconductor layer. A lattice mismatched semiconductor material is selectively grown on the semiconductor layer to fill the trenches, thereby forming embedded lattice mismatched semiconductor material portions in source and drain regions of a transistor. The embedded lattice mismatched semiconductor material portions can be in-situ doped without increasing punch-through. Alternately, a combination of intrinsic selective epitaxy and ion implantation can be employed to form deep source and drain regions.

Abstract translation: 低能量表面通过栅极堆叠的每一侧的沟槽表面的高温退火形成。 半导体层的材料在高温退火期间回流，使得低能表面是与半导体层的表面法线成非正交角的结晶表面。 在半导体层上选择性地生长晶格失配的半导体材料以填充沟槽，从而在晶体管的源极和漏极区域中形成嵌入的晶格失配的半导体材料部分。 嵌入的晶格不匹配的半导体材料部分可以原位掺杂而不增加穿通。 或者，可以采用固有选择性外延和离子注入的组合来形成深的源极和漏极区域。

公开(公告)号：US07960229B2

公开(公告)日：2011-06-14

申请号：US12100598

申请日：2008-04-10

Applicant: Frank Bin Yang ,  Rohit Pal ,  Scott Luning

Inventor： Frank Bin Yang ,  Rohit Pal ,  Scott Luning

IPC: H01L21/336

CPC classification number: H01L29/66628 ,  H01L29/66772 ,  H01L29/78618

Abstract: A metal oxide semiconductor transistor device having a reduced gate height is provided. One embodiment of the device includes a substrate having a layer of semiconductor material, a gate structure overlying the layer of semiconductor material, and source/drain recesses formed in the semiconductor material adjacent to the gate structure, such that remaining semiconductor material is located below the source/drain recesses. The device also includes shallow source/drain implant regions formed in the remaining semiconductor material, and epitaxially grown, in situ doped, semiconductor material in the source/drain recesses.

Abstract translation: 提供了具有减小的栅极高度的金属氧化物半导体晶体管器件。 器件的一个实施例包括具有半导体材料层的衬底，覆盖半导体材料层的栅极结构以及形成在与栅极结构相邻的半导体材料中的源极/漏极凹槽，使得剩余的半导体材料位于 源极/漏极凹槽。 器件还包括在剩余半导体材料中形成的浅源极/漏极注入区域，以及在源极/漏极凹槽中外延生长的原位掺杂的半导体材料。

公开(公告)号：US08664066B2

公开(公告)日：2014-03-04

申请号：US13552722

申请日：2012-07-19

Applicant: Rohit Pal ,  Stephan-Detlef Kronholz

Inventor： Rohit Pal ,  Stephan-Detlef Kronholz

IPC: H01L21/8234

CPC classification number: H01L29/1054 ,  H01L21/823807 ,  H01L21/823857 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66651 ,  H01L29/7833 ,  H01L29/7848 ,  Y02P80/30

Abstract: The present disclosure provides manufacturing techniques in which sophisticated high-k metal gate electrode structures may be formed in an early manufacturing stage on the basis of a selectively applied threshold voltage adjusting semiconductor alloy. In order to reduce the surface topography upon patterning the deposition mask while still allowing the usage of well-established epitaxial growth recipes developed for silicon dioxide-based hard mask materials, a silicon nitride base material may be used in combination with a surface treatment. In this manner, the surface of the silicon nitride material may exhibit a silicon dioxide-like behavior, while the patterning of the hard mask may be accomplished on the basis of highly selective etch techniques.

Abstract translation: 本公开提供了其中可以在选择性施加的阈值电压调节半导体合金的基础上在早期制造阶段中形成复杂的高k金属栅电极结构的制造技术。 为了在图案化沉积掩模的同时减少表面形貌，同时仍允许使用为基于二氧化硅的硬掩模材料开发的良好的外延生长配方，可以将氮化硅基材与表面处理组合使用。 以这种方式，氮化硅材料的表面可以表现出二氧化硅的行为，而硬掩模的图案化可以基于高选择性蚀刻技术来实现。

公开(公告)号：US20120208337A1

公开(公告)日：2012-08-16

申请号：US13456633

申请日：2012-04-26

Applicant: Brian J. Greene ,  William K. Henson ,  Judson R. Holt ,  Michael D. Steigerwalt ,  Kuldeep Amarnath ,  Rohit Pal ,  Johan W. Weijtmans

Inventor： Brian J. Greene ,  William K. Henson ,  Judson R. Holt ,  Michael D. Steigerwalt ,  Kuldeep Amarnath ,  Rohit Pal ,  Johan W. Weijtmans

IPC: H01L21/336

CPC classification number: H01L29/66636 ,  H01L21/3247 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/7848

Abstract: A low energy surface is formed by a high temperature anneal of the surfaces of trenches on each side of a gate stack. The material of the semiconductor layer reflows during the high temperature anneal such that the low energy surface is a crystallographic surface that is at a non-orthogonal angle with the surface normal of the semiconductor layer. A lattice mismatched semiconductor material is selectively grown on the semiconductor layer to fill the trenches, thereby forming embedded lattice mismatched semiconductor material portions in source and drain regions of a transistor. The embedded lattice mismatched semiconductor material portions can be in-situ doped without increasing punch-through. Alternately, a combination of intrinsic selective epitaxy and ion implantation can be employed to form deep source and drain regions.

Abstract translation: 低能量表面通过栅极堆叠的每一侧的沟槽表面的高温退火形成。 半导体层的材料在高温退火期间回流，使得低能表面是与半导体层的表面法线成非正交角的结晶表面。 在半导体层上选择性地生长晶格失配的半导体材料以填充沟槽，从而在晶体管的源极和漏极区域中形成嵌入的晶格失配的半导体材料部分。 嵌入的晶格不匹配的半导体材料部分可以原位掺杂而不增加穿通。 或者，可以采用固有选择性外延和离子注入的组合来形成深的源极和漏极区域。

公开(公告)号：US08119464B2

公开(公告)日：2012-02-21

申请号：US12561638

申请日：2009-09-17

Applicant: Rohit Pal ,  Stephan Waidmann

Inventor： Rohit Pal ,  Stephan Waidmann

IPC: H01L21/84

CPC classification number: H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/78

Abstract: Semiconductor devices with high-K/metal gates are formed with spacers that are substantially resistant to subsequent etching to remove an overlying spacer, thereby avoiding replacement and increasing manufacturing throughput. Embodiments include forming a high-K/metal gate, having an upper surface and side surfaces, over a substrate, e.g., a SOI substrate, and sequentially forming, on the side surfaces of the high-K/metal gate, a first spacer of a non-oxide material, a second spacer, of a material different from that of the first spacer, and a third spacer, of a material different from that of the second spacer. After formation of source and drain regions, e.g., epitaxially grown silicon-germanium, the third spacer is etched with an etchant, such as hot phosphoric acid, to which the second spacer is substantially resistant, thereby avoiding replacement.

Abstract translation: 具有高K /金属栅极的半导体器件由间隔物形成，其具有基本上抵抗后续蚀刻以去除上覆间隔物，从而避免替换并增加制造生产量。 实施例包括在衬底（例如SOI衬底）上形成具有上表面和侧表面的高K /金属栅极，并且在高K /金属栅极的侧表面上依次形成第一间隔物 不同于第一间隔物的材料的非氧化物材料，第二间隔物和与第二间隔物不同的材料的第三间隔物。 在形成源极和漏极区域，例如外延生长的硅 - 锗之后，用蚀刻剂（例如热磷酸）蚀刻第三间隔物，第二间隔物基本上抵抗其上，从而避免更换。

公开(公告)号：US07994014B2

公开(公告)日：2011-08-09

申请号：US12249570

申请日：2008-10-10

Applicant: Frank Bin Yang ,  Rohit Pal ,  Michael J. Hargrove

Inventor： Frank Bin Yang ,  Rohit Pal ,  Michael J. Hargrove

IPC: H01L21/336

CPC classification number: H01L29/66636 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02609 ,  H01L21/02636 ,  H01L29/045 ,  H01L29/41766 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/7848

Abstract: The disclosed subject matter relates to semiconductor transistor devices and associated fabrication techniques that can be utilized to form silicide contacts having an increased effective size, relative to conventional silicide contacts. A semiconductor device fabricated in accordance with the processes disclosed herein includes a layer of semiconductor material and a gate structure overlying the layer of semiconductor material. A channel region is formed in the layer of semiconductor material, the channel region underlying the gate structure. The semiconductor device also includes source and drain regions in the layer of semiconductor material, wherein the channel region is located between the source and drain regions. Moreover, the semiconductor device includes facet-shaped silicide contact areas overlying the source and drain regions.

Abstract translation: 所公开的主题涉及半导体晶体管器件和相关的制造技术，其可以用于形成相对于常规硅化物触点具有增加的有效尺寸的硅化物触点。 根据本文公开的方法制造的半导体器件包括覆盖半导体材料层的半导体材料层和栅极结构。 沟道区形成在半导体材料层中，栅极结构下方的沟道区。 半导体器件还包括半导体材料层中的源区和漏区，其中沟道区位于源区和漏区之间。 此外，半导体器件包括覆盖源极和漏极区域的面形硅化物接触区域。

公开(公告)号：US07939852B2

公开(公告)日：2011-05-10

申请号：US12176835

申请日：2008-07-21

Applicant: Rohit Pal ,  Frank Bin Yang ,  Michael J. Hargrove

Inventor： Rohit Pal ,  Frank Bin Yang ,  Michael J. Hargrove

IPC: H01L31/0328

CPC classification number: H01L29/66636 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/3065 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/7848

Abstract: Semiconductor transistor devices and related fabrication methods are provided. An exemplary transistor device includes a layer of semiconductor material having a channel region defined therein and a gate structure overlying the channel region. Recesses are formed in the layer of semiconductor material adjacent to the channel region, such that the recesses extend asymmetrically toward the channel region. The transistor device also includes stress-inducing semiconductor material formed in the recesses. The asymmetric profile of the stress-inducing semiconductor material enhances carrier mobility in a manner that does not exacerbate the short channel effect.

Abstract translation: 提供半导体晶体管器件及相关制造方法。 示例性晶体管器件包括其中限定有沟道区的半导体材料层和覆盖沟道区的栅极结构。 凹槽在与沟道区相邻的半导体材料层中形成，使得凹槽朝向沟道区不对称地延伸。 晶体管器件还包括形成在凹槽中的应力诱导半导体材料。 应力诱导半导体材料的不对称轮廓以不会加剧短通道效应的方式提高载流子迁移率。