公开(公告)号：US08278165B2

公开(公告)日：2012-10-02

申请号：US12577628

申请日：2009-10-12

Applicant: Rohit Pal ,  Janice Monzet

Inventor： Rohit Pal ,  Janice Monzet

IPC: H01L21/8238

CPC classification number: H01L21/823807 ,  H01L21/31111 ,  H01L21/823878

Abstract: Methods for fabricating semiconductor devices are provided. The methods include providing a semiconductor substrate having pFET and nFET regions, each having active areas and shallow trench isolation. A hardmask layer is formed overlying the semiconductor substrate. A photoresist layer is provided over the hardmask layer. The phoresist layer is patterned. An exposed portion of the hardmask layer is removed from one of the pFET region and nFET region with the patterned photoresist acting as an etch mask to define a masked region and an unmasked region. An epitaxial silicon layer is formed on the active area in the unmasked region. A protective oxide layer is formed overlying the epitaxial silicon layer. The hardmask layer is removed from the masked region with the protective oxide layer protecting the epitaxial silicon layer during such removal step. The protective oxide layer is removed from the epitaxial silicon layer.

Abstract translation: 提供制造半导体器件的方法。 所述方法包括提供具有pFET和nFET区域的半导体衬底，每个具有有源区和浅沟槽隔离。 形成覆盖半导体衬底的硬掩模层。 在硬掩模层上提供光致抗蚀剂层。 光刻胶层被图案化。 硬掩模层的暴露部分从pFET区域和nFET区域中的一个去除，图案化的光致抗蚀剂用作蚀刻掩模以限定掩蔽区域和未掩模区域。 在未掩模区域的有源区域上形成外延硅层。 形成覆盖在外延硅层上的保护性氧化物层。 在这种去除步骤期间，保护氧化层保护外延硅层，从屏蔽区域去除硬掩模层。 从外延硅层去除保护氧化物层。

公开(公告)号：US08664057B2

公开(公告)日：2014-03-04

申请号：US13565970

申请日：2012-08-03

Applicant: Rohit Pal ,  Sven Beyer ,  Andy Wei ,  Richard Carter

Inventor： Rohit Pal ,  Sven Beyer ,  Andy Wei ,  Richard Carter

IPC: H01L21/8238 ,  H01L21/3205 ,  H01L21/4763 ,  H01L21/336 ,  H01L21/28 ,  H01L21/44 ,  H01L21/8234

CPC classification number: H01L21/823807 ,  H01L21/823814 ,  H01L21/823828

Abstract: When forming high-k metal gate electrode structures in transistors of different conductivity type while also incorporating an embedded strain-inducing semiconductor alloy selectively in one type of transistor, superior process uniformity may be accomplished by selectively reducing the thickness of a dielectric cap material of a gate layer stack above the active region of transistors which do not receive the strain-inducing semiconductor alloy. In this case, superior confinement and thus integrity of sensitive gate materials may be accomplished in process strategies in which the sophisticated high-k metal gate electrode structures are formed in an early manufacturing stage, while, in a replacement gate approach, superior process uniformity is achieved upon exposing the surface of a placeholder electrode material.

Abstract translation: 当在不同导电类型的晶体管中形成高k金属栅极电极结构时，同时在一种类型的晶体管中选择性地并入嵌入式应变诱导半导体合金，可以通过选择性地减小介电帽材料的厚度来实现优异的工艺均匀性 栅极层堆叠在不接收应变诱导半导体合金的晶体管的有源区上方。 在这种情况下，可以在早期制造阶段中形成复杂的高k金属栅极电极结构的工艺策略中实现优异的限制和因此敏感栅极材料的完整性，而在替代栅极方法中，优良的工艺均匀性是 在暴露观察者电极材料的表面时实现。

公开(公告)号：US08373228B2

公开(公告)日：2013-02-12

申请号：US12687607

申请日：2010-01-14

Applicant: Bin Yang ,  Rohit Pal ,  Michael Hargrove

Inventor： Bin Yang ,  Rohit Pal ,  Michael Hargrove

IPC: H01L27/12

CPC classification number: H01L21/84 ,  H01L21/845 ,  H01L23/485 ,  H01L27/12 ,  H01L27/1211

Abstract: A method of fabricating a semiconductor device with back side conductive plugs is provided here. The method begins by forming a gate structure overlying a semiconductor-on-insulator (SOI) substrate. The SOI substrate has a support layer, an insulating layer overlying the support layer, an active semiconductor region overlying the insulating layer, and an isolation region outboard of the active semiconductor region. A first section of the gate structure is formed overlying the isolation region and a second section of the gate structure is formed overlying the active semiconductor region. The method continues by forming source/drain regions in the active semiconductor region, and thereafter removing the support layer from the SOI substrate. Next, the method forms conductive plugs for the gate structure and the source/drain regions, where each of the conductive plugs passes through the insulating layer.

Abstract translation: 此处提供制造具有背面导电插头的半导体器件的方法。 该方法通过形成覆盖绝缘体上半导体（SOI）衬底的栅极结构开始。 SOI衬底具有支撑层，覆盖在支撑层上的绝缘层，覆盖绝缘层的有源半导体区域和有源半导体区域外侧的隔离区域。 栅极结构的第一部分形成在隔离区域的上方，栅极结构的第二部分形成在有源半导体区域的上方。 该方法通过在有源半导体区域中形成源极/漏极区域继续，然后从SOI衬底去除支撑层。 接下来，该方法形成用于栅极结构和源极/漏极区域的导电插塞，其中每个导电插塞穿过绝缘层。

公开(公告)号：US20130032893A1

公开(公告)日：2013-02-07

申请号：US13550693

申请日：2012-07-17

Applicant: Rohit Pal ,  George Mulfinger

Inventor： Rohit Pal ,  George Mulfinger

IPC: H01L27/088 ,  H01L21/283

CPC classification number: H01L23/5256 ,  H01L23/485 ,  H01L27/0629 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Gate height scaling in sophisticated semiconductor devices may be implemented without requiring a redesign of non-transistor devices. To this end, the semiconductor electrode material may be adapted in its thickness above active regions and isolation regions that receive the non-transistor devices. Thereafter, the actual patterning of the adapted gate layer stack may be performed so as to obtain gate electrode structures of a desired height for improving, in particular, AC performance without requiring a redesign of the non-transistor devices.

Abstract translation: 可以实现复杂半导体器件中的栅极高度缩放，而不需要重新设计非晶体管器件。 为此，可以将半导体电极材料的厚度适用于有源区域和接收非晶体管器件的隔离区域。 此后，可以执行适合的栅极层堆叠的实际图案化，以获得所需高度的栅电极结构，以改善特别是AC性能，而不需要重新设计非晶体管器件。

公开(公告)号：US20120295420A1

公开(公告)日：2012-11-22

申请号：US13470906

申请日：2012-05-14

Applicant: Rohit Pal ,  Stephan-Detlef Kronholz

Inventor： Rohit Pal ,  Stephan-Detlef Kronholz

IPC: H01L21/20 ,  H01L21/283

CPC classification number: H01L21/76224 ,  H01L21/02057 ,  H01L21/823807 ,  H01L21/823828 ,  H01L21/823878 ,  H01L29/66651 ,  H01L29/7833

Abstract: A thermal oxide may be removed in semiconductor devices prior to performing complex manufacturing processes, such as forming sophisticated gate electrode structures, by using a gaseous process atmosphere instead of a wet chemical etch process, wherein the masking of specific device regions may be accomplished on the basis of a resist mask.

Abstract translation: 在通过使用气体处理气氛而不是湿式化学蚀刻工艺执行复杂的制造工艺（例如形成复杂的栅电极结构）之前，可以在半导体器件中去除热氧化物，其中特定器件区域的掩蔽可以在 抗蚀剂掩模的基础。

公开(公告)号：US20120193727A1

公开(公告)日：2012-08-02

申请号：US13444955

申请日：2012-04-12

Applicant: Richard Carter ,  Martin Trentzsch ,  Sven Beyer ,  Rohit Pal

Inventor： Richard Carter ,  Martin Trentzsch ,  Sven Beyer ,  Rohit Pal

IPC: H01L27/088

CPC classification number: H01L21/823462 ,  H01L21/28176 ,  H01L21/28194 ,  H01L29/513 ,  H01L29/517

Abstract: Sophisticated gate electrode structures may be formed by providing a cap layer including a desired species that may diffuse into the gate dielectric material prior to performing a treatment for stabilizing the sensitive gate dielectric material. In this manner, complex high-k metal gate electrode structures may be formed on the basis of reduced temperatures and doses for a threshold adjusting species compared to conventional strategies. Moreover, a single metal-containing electrode material may be deposited for both types of transistors.

Abstract translation: 复杂的栅极电极结构可以通过在进行用于稳定敏感栅极介电材料的处理之前提供包括可能扩散到栅极电介质材料中的所需物质的覆盖层来形成。 以这种方式，与常规策略相比，可以基于用于阈值调节物质的降低的温度和剂量来形成复杂的高k金属栅电极结构。 此外，可以为两种类型的晶体管沉积单个含金属的电极材料。

公开(公告)号：US08217463B2

公开(公告)日：2012-07-10

申请号：US13021403

申请日：2011-02-04

Applicant: Rohit Pal ,  Michael Hargrove ,  Frank Bin Yang

Inventor： Rohit Pal ,  Michael Hargrove ,  Frank Bin Yang

IPC: H01L29/66

CPC classification number: H01L29/66651 ,  H01L21/28123 ,  H01L21/28194 ,  H01L21/28247 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517

Abstract: Methods for protecting gate stacks during fabrication of semiconductor devices and semiconductor devices fabricated from such methods are provided. Methods for fabricating a semiconductor device include providing a semiconductor substrate having an active region and a shallow trench isolation (STI) region. Epitaxial layer is formed on the active region to define a lateral overhang portion in a divot at the active region/STI region interface. A gate stack is formed having a first gate stack-forming layer overlying the semiconductor substrate. First gate stack-forming layer includes a non-conformal layer of metal gate-forming material which is directionally deposited to form a thinned break portion just below the lateral overhang portion. After the step of forming the gate stack, a first portion of the non-conformal layer is in the gate stack and a second portion is exposed. The thinned break portion at least partially isolates the first and second portions during subsequent etch chemistries.

Abstract translation: 提供了在由这些方法制造的半导体器件和半导体器件的制造期间保护栅极堆叠的方法。 制造半导体器件的方法包括提供具有有源区和浅沟槽隔离（STI）区的半导体衬底。 在有源区上形成外延层，以在有源区/ STI区界面上的边界中限定一个横向伸出部分。 形成具有覆盖在半导体衬底上的第一栅叠层形成层的栅叠层。 第一栅极堆叠形成层包括定向沉积以形成刚好在横向突出部分下方的变薄的断裂部分的非保形层的金属栅极形成材料。 在形成栅极堆叠的步骤之后，非共形层的第一部分在栅极堆叠中并且第二部分被暴露。 减薄断裂部分在随后的蚀刻化学过程中至少部分地隔离第一和第二部分。

公开(公告)号：US07670934B1

公开(公告)日：2010-03-02

申请号：US12359764

申请日：2009-01-26

Applicant: Rohit Pal ,  Frank Bin Yang

Inventor： Rohit Pal ,  Frank Bin Yang

IPC: H01L21/20 ,  H01L21/36

CPC classification number: H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84

Abstract: Methods of fabricating a semiconductor device on and in a semiconductor substrate having a first region and a second region are provided. In accordance with an exemplary embodiment of the invention, a method comprises forming a first gate stack overlying the first region and a second gate stack overlying the second region, etching into the substrate first recesses and second recesses, the first recesses aligned at least to the first gate stack in the first region, and the second recesses aligned at least to the second gate stack in the second region, epitaxially growing a first stress-inducing monocrystalline material in the first and second recesses, removing the first stress-inducing monocrystalline material from the first recesses, and epitaxially growing a second stress-inducing monocrystalline material in the first recesses, wherein the second stress-inducing monocrystalline material has a composition different from the first stress-inducing monocrystalline material.

Abstract translation: 提供了在具有第一区域和第二区域的半导体衬底上和半导体衬底中制造半导体器件的方法。 根据本发明的示例性实施例，一种方法包括形成覆盖第一区域的第一栅极堆叠和覆盖第二区域的第二栅极堆叠，蚀刻到衬底中的第一凹陷和第二凹槽，第一凹陷至少对准 第一栅极堆叠在第一区域中，并且第二凹陷至少对准第二区域中的第二栅极堆叠，在第一和第二凹槽中外延生长第一应力诱导单晶材料，从第一和第二凹槽中去除第一应力诱导单晶材料 第一凹陷，并且在第一凹陷中外延生长第二应力诱导单晶材料，其中第二应力诱导单晶材料具有不同于第一应力诱导单晶材料的组成。

公开(公告)号：US20090280579A1

公开(公告)日：2009-11-12

申请号：US12119196

申请日：2008-05-12

Applicant: Rohit Pal ,  David E. Brown ,  Alok Vaid ,  Kevin Lensing

Inventor： Rohit Pal ,  David E. Brown ,  Alok Vaid ,  Kevin Lensing

IPC: H01L21/66

CPC classification number: H01L29/7848 ,  H01L22/12 ,  H01L22/20 ,  H01L29/66636 ,  H01L29/78

Abstract: A method that includes forming a gate of a semiconductor device on a substrate and forming a recess for an embedded silicon-straining material in source and drain regions for the gate. In this method, a proximity value, which is defined as a distance between the gate and a closest edge of the recess, is controlled by controlling formation of an oxide layer provided beneath the gate. The method can also include feedforward control of process steps in the formation of the recess based upon values measured during the formation of the recess. The method can also apply feedback control to adjust a subsequent recess formation process performed on a subsequent semiconductor device based on the comparison between a measured proximity value and a target proximity value to decrease a difference between a proximity value of the subsequent semiconductor device and the target proximity value.

Abstract translation: 一种方法，包括在衬底上形成半导体器件的栅极，并在栅极的源极和漏极区域中形成嵌入的硅应变材料的凹部。 在该方法中，通过控制形成在栅极下方的氧化物层来控制被定义为栅极和凹部的最近边缘之间的距离的接近值。 该方法还可以包括基于在形成凹部期间测量的值来形成凹部中的工艺步骤的前馈控制。 该方法还可以基于测量的接近度值和目标接近值之间的比较来应用反馈控制来调整对随后的半导体器件执行的随后的凹陷形成处理，以减小随后的半导体器件的接近值与目标之间的差异 接近值。

公开(公告)号：US20080119031A1

公开(公告)日：2008-05-22

申请号：US11562209

申请日：2006-11-21

Applicant: Rohit Pal ,  Igor Peidous ,  David Brown

Inventor： Rohit Pal ,  Igor Peidous ,  David Brown

IPC: H01L21/20 ,  H01L21/36 ,  H01L31/20

CPC classification number: H01L29/7848 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/045 ,  H01L29/165 ,  H01L29/66636

Abstract: A stress enhanced MOS transistor and methods for its fabrication are provided. In one embodiment the method comprises forming a gate electrode overlying and defining a channel region in a monocrystalline semiconductor substrate. A trench having a side surface facing the channel region is etched into the monocrystalline semiconductor substrate adjacent the channel region. The trench is filled with a second monocrystalline semiconductor material having a first concentration of a substitutional atom and with a third monocrystalline semiconductor material having a second concentration of the substitutional atom. The second monocrystalline semiconductor material is epitaxially grown to have a wall thickness along the side surface sufficient to exert a greater stress on the channel region than the stress that would be exerted by a monocrystalline semiconductor material having the second concentration if the trench was filled by the third monocrystalline material alone.

Abstract translation: 提供了一种应力增强型MOS晶体管及其制造方法。 在一个实施例中，该方法包括形成覆盖并限定单晶半导体衬底中的沟道区的栅电极。 具有面向通道区域的侧表面的沟槽被蚀刻到与沟道区域相邻的单晶半导体衬底中。 沟槽填充有具有第一浓度的取代原子的第二单晶半导体材料和具有第二浓度取代原子的第三单晶半导体材料。 第二单晶半导体材料被外延生长以具有沿着侧表面的壁厚，足以在沟道区域施加比由具有第二浓度的单晶半导体材料施加的应力更大的应力，如果沟槽由 第三单晶材料。