公开(公告)号：US07075155B1

公开(公告)日：2006-07-11

申请号：US10866114

申请日：2004-06-14

申请人： Mario M. Pelella

发明人： Mario M. Pelella

IPC分类号： H01L23/62

CPC分类号： H01L29/7436 ,  H01L27/0259 ,  H01L2924/0002 ,  H01L2924/00

摘要： A structure for protecting a semiconductor circuit from electrostatic discharge is provided. The structure comprises a semiconductor substrate of a first conductivity type having two wells of a second conductivity type spaced laterally apart. The wells each comprise a first portion having a first concentration of an impurity of the second conductivity type and a second portion comprising source and drain regions having a second concentration of an impurity of the second conductivity type. The second concentration is greater than the first concentration. The wells are implanted in the substrate of a silicon-on-insulator semiconductor device. Conductive plugs extend through the silicon and insulator layers and make electrical contact with the wells, allowing the dissipation of excess current and heat into the semiconductor substrate.

摘要翻译： 提供了一种用于保护半导体电路免受静电放电的结构。 该结构包括具有第二导电类型的具有间隔开间隔的两个阱的第一导电类型的半导体衬底。 每个孔各自包括具有第二导电类型的杂质的第一浓度的第一部分和包含具有第二导电类型的杂质的第二浓度的源区和漏区的第二部分。 第二浓度大于第一浓度。 将阱注入到绝缘体上硅半导体器件的衬底中。 导电插头延伸穿过硅和绝缘体层，并与阱电接触，从而将过剩的电流和热量散发到半导体衬底中。

公开(公告)号：US06700430B1

公开(公告)日：2004-03-02

申请号：US10188173

申请日：2002-08-20

申请人： Mario M. Pelella ,  Srikanth Sundararajan

发明人： Mario M. Pelella ,  Srikanth Sundararajan

IPC分类号： H03K1704

CPC分类号： H01L27/1203 ,  H01L29/78612 ,  H03K3/012

摘要： A method for reducing the time for a partially depleted/silicon-on-insulator (PD/SOI) based circuit to reach a dynamic steady state pre-conditions the PD/SOI-based circuit by initially charging the circuit at a voltage greater than the normal operating voltage. The circuit is then charged at the normal operating voltage after a predetermined amount of time. By pre-conditioning the circuit in this manner, the amount of time required for the PD/SOI transistors of the circuit to reach their dynamic steady state (DSS) condition is shortened.

摘要翻译： 一种减少部分耗尽/绝缘体上（基于硅）的电路达到动态稳态的时间的方法通过以大于该电压的电压对电路进行初始充电来预先调节基于PD / SOI的电路 正常工作电压。 然后在预定时间量之后，在正常工作电压下对电路进行充电。 通过以这种方式对电路进行预调节，电路的PD / SOI晶体管达到其动态稳态（DSS）条件所需的时间被缩短。

公开(公告)号：US06642119B1

公开(公告)日：2003-11-04

申请号：US10215171

申请日：2002-08-08

申请人： Mario M. Pelella ,  Shankar Sinha ,  Simon S. Chan

发明人： Mario M. Pelella ,  Shankar Sinha ,  Simon S. Chan

IPC分类号： H01L21336

CPC分类号： H01L29/66507 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/458 ,  H01L29/66757 ,  H01L29/78612 ,  H01L29/78621 ,  Y10S438/952

摘要： The present invention relates to a method of forming a transistor and a transistor structure. The invention comprises forming the transistor using a double silicide process which reduces resistance and reduces the floating-body-effect when employed in conjunction with SOI type device architecture.

摘要翻译： 本发明涉及一种形成晶体管和晶体管结构的方法。 本发明包括使用双硅化物工艺来形成晶体管，当与SOI型器件结构结合使用时，其降低电阻并降低浮体效应。

公开(公告)号：US06323522B1

公开(公告)日：2001-11-27

申请号：US09227695

申请日：1999-01-08

申请人： Michael J. Hargrove ,  Mario M. Pelella ,  Steven H. Voldman

发明人： Michael J. Hargrove ,  Mario M. Pelella ,  Steven H. Voldman

IPC分类号： H01L2900

CPC分类号： H01L27/1203 ,  H01L27/0266 ,  H01L29/4908 ,  H01L29/78615 ,  H01L29/78696 ,  H01L2924/0002 ,  H01L2924/00

摘要： A SOI field effect transistor structure providing ESD protection. The structure has a source, a drain, a body, and a gate. The gate is formed from a thick oxide layer and a metal contact. The gate is formed during the BEOL process. The transistor may be a p-type transistor or an n-type transistor. The transistor may have its drain tied to either the gate, the body, or both the gate and body. When used as a protection device, the drain is tied to a signal pad and the source is tied to a potential reference.

摘要翻译： 提供ESD保护的SOI场效应晶体管结构。 该结构具有源，漏，体和门。 栅极由厚的氧化物层和金属接触形成。 门在BEOL过程中形成。 晶体管可以是p型晶体管或n型晶体管。 晶体管可以将其漏极连接到栅极，主体或栅极和主体两者。 当用作保护装置时，漏极连接到信号焊盘，源极连接到潜在的参考电压。

公开(公告)号：US07986008B2

公开(公告)日：2011-07-26

申请号：US12413185

申请日：2009-03-27

申请人： Ali Icel ,  Qiang Chen ,  Mario M. Pelella

发明人： Ali Icel ,  Qiang Chen ,  Mario M. Pelella

IPC分类号： H01L27/12

CPC分类号： H01L27/1203 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/84

摘要： SOI semiconductor components and methods for their fabrication are provided wherein the SOI semiconductor components include an MOS transistor in the supporting semiconductor substrate. In accordance with one embodiment the component comprises a semiconductor on insulator (SOI) substrate having a first semiconductor layer, a layer of insulator on the first semiconductor layer, and a second semiconductor layer overlying the layer of insulator. The component includes source and drain regions of a first conductivity type and first doping concentration in the first semiconductor layer. A channel region of a second conductivity type is defined between the source and drain regions. A gate insulator and gate electrode overlie the channel region. A drift region of the first conductivity type is located between the channel region and the drain region, the drift region having a second doping concentration less than the first doping concentration of the first conductivity determining dopant.

摘要翻译： 提供SOI半导体元件及其制造方法，其中SOI半导体元件包括支撑半导体衬底中的MOS晶体管。 根据一个实施例，该部件包括具有第一半导体层，第一半导体层上的绝缘体层和覆盖绝缘体层的第二半导体层的绝缘体上半导体衬底（SOI）衬底。 该部件包括第一导电类型的源区和漏区以及第一半导体层中的第一掺杂浓度。 在源区和漏区之间限定第二导电类型的沟道区。 栅极绝缘体和栅极电极覆盖沟道区域。 第一导电类型的漂移区域位于沟道区域和漏极区域之间，漂移区域具有小于第一导电性确定掺杂剂的第一掺杂浓度的第二掺杂浓度。

公开(公告)号：US07741164B2

公开(公告)日：2010-06-22

申请号：US12033060

申请日：2008-02-19

申请人： Mario M. Pelella

发明人： Mario M. Pelella

IPC分类号： H01L21/84

CPC分类号： H01L21/823481 ,  H01L21/28123 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/66128 ,  H01L29/8611

摘要： A method is provided for fabricating a semiconductor on insulator (SOI) device. The method includes, in one embodiment, providing a monocrystalline silicon substrate having a monocrystalline silicon layer overlying a monocrystalline silicon substrate and separated therefrom by a dielectric layer. A well region is ion implanted in the monocrystalline silicon substrate. A gate electrode material is deposited overlying the monocrystalline silicon layer. The gate electrode material is photolithographically patterned and etched using a minimum lithography feature size to form a first gate electrode, a second gate electrode and a spacer having the minimum lithography feature size. The gate electrode material is then isotropically etched to reduce the width of the first gate electrode, the second gate electrode and the spacer.

摘要翻译： 提供了一种用于制造绝缘体上半导体（SOI）器件的方法。 在一个实施例中，该方法包括提供具有单晶硅层的单晶硅衬底，该单晶硅层覆盖单晶硅衬底，并通过电介质层与其分离。 在单晶硅衬底中离子注入阱区。 沉积在单晶硅层上的栅电极材料。 使用最小光刻特征尺寸对光栅图案化和蚀刻栅电极材料以形成具有最小光刻特征尺寸的第一栅电极，第二栅电极和间隔物。 然后各向同性蚀刻栅电极材料，以减小第一栅电极，第二栅电极和间隔物的宽度。

公开(公告)号：US07531403B2

公开(公告)日：2009-05-12

申请号：US11538001

申请日：2006-10-02

申请人： Ali Icel ,  Qiang Chen ,  Mario M. Pelella

发明人： Ali Icel ,  Qiang Chen ,  Mario M. Pelella

IPC分类号： H01L21/8238

CPC分类号： H01L27/1203 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/84

摘要： SOI semiconductor components and methods for their fabrication are provided wherein the SOI semiconductor components include an MOS transistor in the supporting semiconductor substrate. In accordance with one embodiment the component comprises a semiconductor on insulator (SOI) substrate having a first semiconductor layer, a layer of insulator on the first semiconductor layer, and a second semiconductor layer overlying the layer of insulator. The component includes source and drain regions of first conductivity type and first doping concentration in the first semiconductor layer. A channel region of second conductivity type is defined between the source and drain regions. A gate insulator and gate electrode overlie the channel region. A drift region of first conductivity type is located between the channel region and the drain region, the drift region having a second doping concentration less than the first doping concentration of first conductivity determining dopant.

摘要翻译： 提供SOI半导体元件及其制造方法，其中SOI半导体元件包括支撑半导体衬底中的MOS晶体管。 根据一个实施例，该部件包括具有第一半导体层，第一半导体层上的绝缘体层和覆盖绝缘体层的第二半导体层的绝缘体上半导体衬底（SOI）衬底。 该部件包括第一半导体层中的第一导电类型和第一掺杂浓度的源区和漏区。 在源区和漏区之间限定第二导电类型的沟道区。 栅极绝缘体和栅极电极覆盖沟道区域。 第一导电类型的漂移区域位于沟道区域和漏极区域之间，漂移区域具有小于第一导电性确定掺杂剂的第一掺杂浓度的第二掺杂浓度。

公开(公告)号：US20090073758A1

公开(公告)日：2009-03-19

申请号：US11857757

申请日：2007-09-19

申请人： Gregory G. Freeman ,  Qingqing Liang ,  Mario M. Pelella ,  Carl J. Radens ,  Huicai Zhong ,  Huilong Zhu

发明人： Gregory G. Freeman ,  Qingqing Liang ,  Mario M. Pelella ,  Carl J. Radens ,  Huicai Zhong ,  Huilong Zhu

IPC分类号： G11C11/34 ,  H01L21/00

CPC分类号： G11C11/412

摘要： The embodiments of the invention provide SRAM cells with asymmetric floating-body pass-gate transistors. More specifically, a semiconductor device includes an SRAM cell, a first pass-gate transistor, and a second pass-gate transistor. The first pass-gate transistor is connected to a first side of the SRAM cell, wherein the first pass-gate transistor comprises a first drain region and a first source region. The second pass-gate transistor is connected to a second side of the SRAM cell, wherein the second side is opposite the first side. The second pass-gate transistor comprises a second source region and a second drain region. Furthermore, the first source region and/or the second source region comprise a xenon implant. The first drain region and the second drain region each lack a xenon implant.

摘要翻译： 本发明的实施例提供具有非对称浮体通过栅极晶体管的SRAM单元。 更具体地，半导体器件包括SRAM单元，第一通过栅极晶体管和第二通过栅极晶体管。 第一栅极晶体管连接到SRAM单元的第一侧，其中第一栅极晶体管包括第一漏极区域和第一源极区域。 第二通栅晶体管连接到SRAM单元的第二侧，其中第二侧与第一侧相对。 第二通栅晶体管包括第二源区和第二漏区。 此外，第一源区和/或第二源区包括氙植入物。 第一漏区和第二漏区各自缺少氙植入物。

公开(公告)号：US07494885B1

公开(公告)日：2009-02-24

申请号：US10818155

申请日：2004-04-05

申请人： Mario M. Pelella ,  Darin A. Chan ,  Kei-Leong Ho ,  Lu You

发明人： Mario M. Pelella ,  Darin A. Chan ,  Kei-Leong Ho ,  Lu You

IPC分类号： H01L21/00

CPC分类号： H01L29/6659 ,  H01L29/41775 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/7833

摘要： According to one exemplary embodiment, a method for forming a field effect transistor on a substrate comprises a step of forming disposable spacers adjacent to a gate stack situated on the substrate, where the disposable spacers comprise amorphous carbon. The disposable spacers can be formed by depositing a layer of amorphous carbon on the gate stack and anisotropically etching the layer of amorphous carbon. The method further comprises forming source and drain regions in the substrate, where the source and drain regions are situated adjacent to the disposable spacers. According to this exemplary embodiment, the method further comprises removing the disposable spacers, where the removal of the disposable spacers causes substantially no gouging in the substrate. The disposable spacers can be removed by using a dry etch process. The method can further comprise forming extension regions in the substrate adjacent to the gate stack prior to forming the disposable spacers.

摘要翻译： 根据一个示例性实施例，用于在衬底上形成场效应晶体管的方法包括形成邻近位于衬底上的栅极堆叠的一次性间隔物的步骤，其中一次性间隔物包括无定形碳。 可以通过在栅极堆叠上沉积无定形碳层并且各向异性地蚀刻无定形碳层来形成一次性间隔物。 该方法还包括在衬底中形成源极和漏极区域，其中源极区域和漏极区域邻近一次性间隔物定位。 根据该示例性实施例，该方法还包括去除一次性间隔件，其中一次性间隔件的移除基本上不引起基板中的气刨。 可以通过使用干法蚀刻工艺去除一次性间隔物。 该方法还可以包括在形成一次性间隔件之前在邻近栅极堆叠的基板中形成延伸区域。

公开(公告)号：US07439127B2

公开(公告)日：2008-10-21

申请号：US11409362

申请日：2006-04-20

申请人： Mario M. Pelella

发明人： Mario M. Pelella

IPC分类号： H01L21/8242

CPC分类号： H01L27/0629 ,  H01L21/84 ,  H01L27/1203 ,  H01L28/55

摘要： A method is provided for fabricating a semiconductor component that includes a capacitor having a high capacitance per unit area. The component is formed in and on a semiconductor on insulator (SOI) substrate having a first semiconductor layer, a layer of insulator on the first semiconductor layer, and a second semiconductor layer overlying the layer of insulator. The method comprises forming a first capacitor electrode in the first semiconductor layer and depositing a dielectric layer comprising Ba1-xCaxTi1-yZryO3 overlying the first capacitor electrode. A conductive material is deposited and patterned to form a second capacitor electrode overlying the dielectric layer, thus forming a capacitor having a high dielectric constant dielectric. An MOS transistor in then formed in a portion of the second semiconductor layer, the MOS transistor, and especially the gate dielectric of the MOS transistor, formed independently of forming the capacitor and electrically isolated from the capacitor.

摘要翻译： 提供了一种用于制造半导体元件的方法，该半导体元件包括具有每单位面积的高电容的电容器。 该部件形成在具有第一半导体层，第一半导体层上的绝缘体层和覆盖在绝缘体层上的第二半导体层的绝缘体上半导体（SOI）衬底中和之上。 该方法包括在第一半导体层中形成第一电容器电极，并沉积包含Ba 1-x Ti x Ti 1-y的介电层， 在第一电容器电极上覆盖的第三电极。 沉积并图案化导电材料，以形成覆盖介电层的第二电容器电极，从而形成具有高介电常数电介质的电容器。 然后形成在第二半导体层的一部分中的MOS晶体管，MOS晶体管，特别是MOS晶体管的栅极电介质，独立于形成电容器并与电容器电隔离形成。