利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

36 条记录 (耗时 0.026 秒)

    Structure and methods for process integration in vertical DRAM cell fabrication
    23.
    发明授权
    Structure and methods for process integration in vertical DRAM cell fabrication 有权
    垂直DRAM单元制造过程集成的结构和方法

    公开(公告)号：US06790739B2

    公开(公告)日：2004-09-14

    申请号：US10249997

    申请日：2003-05-27

    申请人： Rajeev Malik ,  Larry Nesbit ,  Jochen Beintner ,  Rama Divakaruni

    发明人： Rajeev Malik ,  Larry Nesbit ,  Jochen Beintner ,  Rama Divakaruni

    IPC分类号： H01L2120

    CPC分类号： H01L27/10894 ,  H01L21/76224 ,  H01L27/10861

    摘要： A method for processing a semiconductor memory device is disclosed, the memory device including an array area and a support area thereon. In an exemplary embodiment of the invention, the method includes removing, from the array area, an initial pad nitride material formed on the device. The initial pad nitride material in the support area, however, is still maintained. Active device areas are then formed within the array area, wherein the initial pad nitride maintained in the support area helps to protect the support area from wet etch processes implemented during the formation of active device areas within the array area.

    摘要翻译： 公开了一种用于处理半导体存储器件的方法，所述存储器件包括阵列区域和其上的支撑区域。 在本发明的示例性实施例中，该方法包括从阵列区域去除在器件上形成的初始衬垫氮化物材料。 然而，支撑区域中的初始衬垫氮化物材料仍然保持。 然后在阵列区域内形成有源器件区域，其中保持在支撑区域中的初始衬垫氮化物有助于保护支撑区域免受在阵列区域内形成有源器件区域期间实现的湿蚀刻工艺。

    Line mask defined active areas for 8F2 dram cells with folded bit lines and deep trench patterns
    24.
    发明申请
    Line mask defined active areas for 8F2 dram cells with folded bit lines and deep trench patterns 有权
    线路掩模定义了具有折叠位线和深沟槽图案的8F2显示单元的有源区域

    公开(公告)号：US20050176197A1

    公开(公告)日：2005-08-11

    申请号：US10774827

    申请日：2004-02-09

    申请人： Rolf Weis ,  Ramachandra Divakaruni ,  Larry Nesbit

    发明人： Rolf Weis ,  Ramachandra Divakaruni ,  Larry Nesbit

    IPC分类号： H01L21/8242

    CPC分类号： H01L27/10867 ,  H01L27/10864

    摘要： A memory cell is formed for a memory cell array that is comprised of a plurality of the memory cells arranged in rows and columns. Deep trenches having sidewalls is formed within a semiconductor substrate. A buried plate region adjoining a deep trench is formed within the semiconductor substrate, and a dielectric film is formed along the sidewalls of the deep trench. A masking layer is patterned such that a portion of the dielectric film is covered by the masking layer and a remaining portion of the dielectric film is exposed. An upper region of the exposed portion of the dielectric film is removed such that a trench collar is formed along a middle portion of a side of the deep trench. The deep trench is partly filled with doped polysilicon. The dopants in the polysilicon diffuse through the side of the deep trench into adjoining regions of the semiconductor substrate during subsequent thermal processing steps to form a buried strap region along a side of the deep trench. The semiconductor substrate is patterned and etched to form at least one isolation trench that adjoins the isolation trench and two of the deep trenches and includes a buried strap region. The patterning uses a mask comprised of a lines and spaces pattern such that at least one active area is defined by the isolation trench and by the deep trench. Each of the lines and the spaces extends across the memory cell array.

    摘要翻译： 为存储单元阵列形成存储单元，存储单元阵列由以行和列排列的多个存储单元组成。 具有侧壁的深沟槽形成在半导体衬底内。 在半导体衬底内形成与深沟槽相邻的掩埋板区域，沿着深沟槽的侧壁形成电介质膜。 图案化掩模层，使得电介质膜的一部分被掩蔽层覆盖，并且电介质膜的剩余部分被暴露。 去除电介质膜的暴露部分的上部区域，使得沿着深沟槽的一侧的中间部分形成沟槽套环。 深沟槽部分填充有掺杂多晶硅。 在随后的热处理步骤期间，多晶硅中的掺杂剂通过深沟槽的侧面扩散到半导体衬底的相邻区域中，以沿着深沟槽的一侧形成掩埋带区域。 对半导体衬底进行图案化和蚀刻以形成邻接隔离沟槽和两个深沟槽中的至少一个隔离沟槽并且包括掩埋带区域。 图案化使用由线和空间图案组成的掩模，使得至少一个有源区域由隔离沟槽和深沟槽限定。 每个行和空格都延伸穿过存储单元阵列。

    Semiconductor fuses and antifuses in vertical DRAMS
    26.
    发明授权
    Semiconductor fuses and antifuses in vertical DRAMS 有权
    垂直DRAMS中的半导体熔断器和反熔丝

    公开(公告)号：US06509624B1

    公开(公告)日：2003-01-21

    申请号：US09675246

    申请日：2000-09-29

    申请人： Carl J. Radens ,  Wolfgang Bergner ,  Rama Divakaruni ,  Larry Nesbit

    发明人： Carl J. Radens ,  Wolfgang Bergner ,  Rama Divakaruni ,  Larry Nesbit

    IPC分类号： H01L2900

    CPC分类号： H01L27/10861 ,  H01L23/5252 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A structure and process for semiconductor fuses and antifuses in vertical DRAMS provides fuses and antifuses in trench openings formed within a semiconductor substrate. Vertical transistors may be formed in other of the trench openings formed within the semiconductor substrate. The fuse is formed including a semiconductor plug formed within an upper portion of the trench opening and includes conductive leads contacting the semiconductor plug. The antifuse is formed including a semiconductor plug formed within an upper portion of the trench opening and includes conductive leads formed over the semiconductor plug, at least one conductive lead isolated from the semiconductor plug by an antifuse dielectric. Each of the fuse and antifuse are fabricated using a sequence of process operations also used to simultaneously fabricate vertical transistors according to vertical DRAM technology.

    摘要翻译： 垂直DRAMS中的半导体熔丝和反熔丝的结构和工艺在半导体衬底内形成的沟槽开口中提供熔丝和反熔丝。 垂直晶体管可以形成在形成在半导体衬底内的其它沟槽开口中。 熔丝形成包括形成在沟槽开口的上部内的半导体插塞，并且包括接触半导体插头的导电引线。 反熔丝形成包括形成在沟槽开口的上部内的半导体插塞，并且包括形成在半导体插头上的导电引线，至少一个导电引线，其通过反熔丝绝缘体与半导体插塞隔离。 每个熔丝和反熔丝都是使用一系列工艺操作来制造的，这些工序也用于根据垂直DRAM技术同时制造垂直晶体管。

    Line mask defined active areas for 8F2 DRAM cells with folded bit lines and deep trench patterns
    28.
    发明授权
    Line mask defined active areas for 8F2 DRAM cells with folded bit lines and deep trench patterns 有权
    线掩模定义了具有折叠位线和深沟槽图案的8F2 DRAM单元的有源区

    公开(公告)号：US07244980B2

    公开(公告)日：2007-07-17

    申请号：US10774827

    申请日：2004-02-09

    申请人： Rolf Weis ,  Ramachandra Divakaruni ,  Larry Nesbit

    发明人： Rolf Weis ,  Ramachandra Divakaruni ,  Larry Nesbit

    IPC分类号： H01L29/94

    CPC分类号： H01L27/10867 ,  H01L27/10864

    摘要： A memory cell is formed for a memory cell array that is comprised of a plurality of the memory cells arranged in rows and columns. Deep trenches having sidewalls is formed within a semiconductor substrate. A buried plate region adjoining a deep trench is formed within the semiconductor substrate, and a dielectric film is formed along the sidewalls of the deep trench. A masking layer is patterned such that a portion of the dielectric film is covered by the masking layer and a remaining portion of the dielectric film is exposed. An upper region of the exposed portion of the dielectric film is removed such that a trench collar is formed along a middle portion of a side of the deep trench. The deep trench is partly filled with doped polysilicon. The dopants in the polysilicon diffuse through the side of the deep trench into adjoining regions of the semiconductor substrate during subsequent thermal processing steps to form a buried strap region along a side of the deep trench. The semiconductor substrate is patterned and etched to form at least one isolation trench that adjoins the isolation trench and two of the deep trenches and includes a buried strap region. The patterning uses a mask comprised of a lines and spaces pattern such that at least one active area is defined by the isolation trench and by the deep trench. Each of the lines and the spaces extends across the memory cell array.

    摘要翻译： 为存储单元阵列形成存储单元，存储单元阵列由以行和列排列的多个存储单元组成。 具有侧壁的深沟槽形成在半导体衬底内。 在半导体衬底内形成与深沟槽相邻的掩埋板区域，沿着深沟槽的侧壁形成电介质膜。 图案化掩模层，使得电介质膜的一部分被掩蔽层覆盖，并且电介质膜的剩余部分被暴露。 去除电介质膜的暴露部分的上部区域，使得沿着深沟槽的一侧的中间部分形成沟槽套环。 深沟槽部分填充有掺杂多晶硅。 在随后的热处理步骤期间，多晶硅中的掺杂剂通过深沟槽的侧面扩散到半导体衬底的相邻区域中，以沿着深沟槽的一侧形成掩埋带区域。 对半导体衬底进行图案化和蚀刻以形成邻接隔离沟槽和两个深沟槽中的至少一个隔离沟槽并且包括掩埋带区域。 图案化使用由线和空间图案组成的掩模，使得至少一个有源区域由隔离沟槽和深沟槽限定。 每个行和空格都延伸穿过存储单元阵列。

    Inclusion of low-k dielectric material between bit lines
    29.
    发明授权
    Inclusion of low-k dielectric material between bit lines 有权
    在位线之间包含低k电介质材料

    公开(公告)号：US07125790B2

    公开(公告)日：2006-10-24

    申请号：US10689233

    申请日：2003-10-20

    申请人： Kia Seng Low ,  Larry Nesbit ,  George C. Feng

    发明人： Kia Seng Low ,  Larry Nesbit ,  George C. Feng

    IPC分类号： H01L21/4763

    CPC分类号： H01L27/10864 ,  H01L27/10885

    摘要： Low-k dielectric materials are incorporated as an insulator material between bit lines and an inter-level dielectric material. The device is first processed in a known manner, up to and including the deposition and anneal of the bit line metal, using a higher dielectric constant material that can withstand the higher temperature process steps as the insulator between the bit lines. Then, the higher dielectric constant material is removed using an etch that is selective to the bit line metal, and the low-k dielectric material is deposited. The low-k material may then be planarized to the top of the bit lines, and further low-k material deposited as an inter-level dielectric. Alternatively, sufficient low-k material is deposited in a single step to both fill the gaps between the bit lines as well as serve as an inter-level dielectric, and then the low-k dielectric material is planarized. Standard processing may then be carried out.

    摘要翻译： 低k电介质材料作为位线和层间电介质材料之间的绝缘体材料并入。 首先使用能够承受作为位线之间的绝缘体的较高温度工艺步骤的较高介电常数材料，以已知的方式处理器件，直到并包括位线金属的沉积和退火。 然后，使用对位线金属有选择性的蚀刻去除较高的介电常数材料，并沉积低介电常数材料。 然后可以将低k材料平面化到位线的顶部，并且将另外的低k材料沉积为层间电介质。 或者，在单个步骤中沉积足够的低k材料，以填充位线之间的间隙以及用作层间电介质，然后将低k电介质材料平坦化。 然后可以执行标准处理。

    Inclusion of low-k dielectric material between bit lines
    30.
    发明申请
    Inclusion of low-k dielectric material between bit lines 有权
    在位线之间包含低k电介质材料

    公开(公告)号：US20050085096A1

    公开(公告)日：2005-04-21

    申请号：US10689233

    申请日：2003-10-20

    申请人： Kia Low ,  Larry Nesbit ,  George Feng

    发明人： Kia Low ,  Larry Nesbit ,  George Feng

    IPC分类号： H01L21/469 ,  H01L21/768 ,  H01L21/8242

    CPC分类号： H01L27/10864 ,  H01L27/10885

    摘要： Low-k dielectric materials are incorporated as an insulator material between bit lines and an inter-level dielectric material. The device is first processed in a known manner, up to and including the deposition and anneal of the bit line metal, using a higher dielectric constant material that can withstand the higher temperature process steps as the insulator between the bit lines. Then, the higher dielectric constant material is removed using an etch that is selective to the bit line metal, and the low-k dielectric material is deposited. The low-k material may then be planarized to the top of the bit lines, and further low-k material deposited as an inter-level dielectric. Alternatively, sufficient low-k material is deposited in a single step to both fill the gaps between the bit lines as well as serve as an inter-level dielectric, and then the low-k dielectric material is planarized. Standard processing may then be carried out.

    摘要翻译： 低k电介质材料作为位线和层间电介质材料之间的绝缘体材料并入。 首先使用能够承受作为位线之间的绝缘体的较高温度工艺步骤的较高介电常数材料，以已知的方式处理器件，直到并包括位线金属的沉积和退火。 然后，使用对位线金属有选择性的蚀刻去除较高的介电常数材料，并沉积低介电常数材料。 然后可以将低k材料平面化到位线的顶部，并且将另外的低k材料沉积为层间电介质。 或者，在单个步骤中沉积足够的低k材料，以填充位线之间的间隙以及用作层间电介质，然后将低k电介质材料平坦化。 然后可以执行标准处理。