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93 条记录 (耗时 0.033 秒)

    Sophisticated gate electrode structures formed by cap layer removal with reduced loss of embedded strain-inducing semiconductor material
    21.
    发明授权
    Sophisticated gate electrode structures formed by cap layer removal with reduced loss of embedded strain-inducing semiconductor material 有权
    通过盖层去除形成的复杂的栅极电极结构，并减少嵌入的应变诱导半导体材料的损耗

    公开(公告)号：US08765559B2

    公开(公告)日：2014-07-01

    申请号：US13358101

    申请日：2012-01-25

    申请人： Stephan Kronholz ,  Gunda Beernink ,  Markus Lenski ,  Frank Seliger ,  Frank Richter

    发明人： Stephan Kronholz ,  Gunda Beernink ,  Markus Lenski ,  Frank Seliger ,  Frank Richter

    IPC分类号： H01L21/336

    CPC分类号： H01L21/823807 ,  H01L21/823814

    摘要： When forming sophisticated gate electrode structures, such as high-k metal gate electrode structures, an appropriate encapsulation may be achieved, while also undue material loss of a strain-inducing semiconductor material that is provided in one type of transistor may be avoided. To this end, the patterning of the protective spacer structure prior to depositing the strain-inducing semiconductor material may be achieved for each type of transistor on the basis of the same process flow, while, after the deposition of the strain-inducing semiconductor material, an etch stop layer may be provided so as to preserve integrity of the active regions.

    摘要翻译： 当形成诸如高k金属栅电极结构的复杂的栅电极结构时，可以实现适当的封装，同时也可以避免在一种晶体管中提供的应变诱导半导体材料的不适当的材料损耗。 为此，可以在沉积应变诱导半导体材料之前对保护间隔物结构进行图案化，其基于相同的工艺流程，对于每种类型的晶体管，在应变诱导半导体材料沉积之后， 可以提供蚀刻停止层，以便保持活性区域的完整性。

    Enhanced cap layer integrity in a high-K metal gate stack by using a hard mask for offset spacer patterning
    25.
    发明授权
    Enhanced cap layer integrity in a high-K metal gate stack by using a hard mask for offset spacer patterning 有权
    通过使用用于偏移间隔物图案化的硬掩模，在高K金属栅极堆叠中增强了覆盖层的完整性

    公开(公告)号：US07981740B2

    公开(公告)日：2011-07-19

    申请号：US12821583

    申请日：2010-06-23

    申请人： Markus Lenski ,  Kerstin Ruttloff ,  Martin Mazur ,  Frank Seliger ,  Ralf Otterbach

    发明人： Markus Lenski ,  Kerstin Ruttloff ,  Martin Mazur ,  Frank Seliger ,  Ralf Otterbach

    IPC分类号： H01L21/8238 ,  H01L21/336

    CPC分类号： H01L21/823864 ,  H01L21/823807 ,  H01L29/7843

    摘要： When forming transistor elements on the basis of sophisticated high-k metal gate structures, the efficiency of a replacement gate approach may be enhanced by more efficiently adjusting the gate height of transistors of different conductivity type when the dielectric cap layers of transistors may have experienced a different process history and may thus require a subsequent adaptation of the final cap layer thickness in one type of the transistors. For this purpose, a hard mask material may be used during a process sequence for forming offset spacer elements in one gate electrode structure while covering another gate electrode structure.

    摘要翻译： 当在复杂的高k金属栅极结构的基础上形成晶体管元件时，可以通过更有效地调节不同导电类型的晶体管的栅极高度来增强置换栅极方法的效率，当晶体管的介质盖层可能经历了 因此可能需要在一种类型的晶体管中随后适应最终的盖层厚度。 为此，可以在用于在一个栅电极结构中形成偏移间隔元件同时覆盖另一栅电极结构的处理顺序期间使用硬掩模材料。

    METHOD OF OPTIMIZING SIDEWALL SPACER SIZE FOR SILICIDE PROXIMITY WITH IN-SITU CLEAN
    27.
    发明申请
    METHOD OF OPTIMIZING SIDEWALL SPACER SIZE FOR SILICIDE PROXIMITY WITH IN-SITU CLEAN 有权
    利用现场清洁优化硅酸盐污染物尺寸的方法

    公开(公告)号：US20090286389A1

    公开(公告)日：2009-11-19

    申请号：US12122840

    申请日：2008-05-19

    申请人： David G. Farber ,  Fred Hause ,  Markus Lenski ,  Anthony C. Mowry

    发明人： David G. Farber ,  Fred Hause ,  Markus Lenski ,  Anthony C. Mowry

    IPC分类号： H01L21/3205 ,  H01L21/4763

    CPC分类号： H01L29/665 ,  H01L21/28052 ,  H01L29/6653 ,  H01L29/78

    摘要： A method that includes forming a gate of a semiconductor device on a substrate, and etching sidewall spacers on sides of the gate to provide a proximity value, where the proximity value is defined as a distance between the gate and an edge of a performance-enhancing region. The sidewall spacers are used to define the edge of the region during formation of the region in the substrate. The method also includes pre-cleaning the gate and the substrate in preparation for formation of the region, where the etching and the pre-cleaning are performed in a continuous vacuum.

    摘要翻译： 一种方法，包括在衬底上形成半导体器件的栅极，并且蚀刻栅极侧面上的侧壁间隔物以提供接近值，其中接近值被定义为栅极与性能增强的边缘之间的距离 地区。 侧壁间隔件用于在衬底中形成区域期间限定区域的边缘。 该方法还包括预先清洁栅极和基板以准备形成区域，其中在连续真空中进行蚀刻和预清洁。

    Methods of Forming Metal Silicide Regions on Semiconductor Devices
    28.
    发明申请
    Methods of Forming Metal Silicide Regions on Semiconductor Devices 有权
    在半导体器件上形成金属硅化物区域的方法

    公开(公告)号：US20130157450A1

    公开(公告)日：2013-06-20

    申请号：US13331842

    申请日：2011-12-20

    申请人： Clemens Fitz ,  Peter Baars ,  Markus Lenski

    发明人： Clemens Fitz ,  Peter Baars ,  Markus Lenski

    IPC分类号： H01L21/283

    CPC分类号： H01L21/76897 ,  H01L21/28518 ,  H01L21/28556 ,  H01L21/76814 ,  H01L29/41783 ,  H01L29/66545

    摘要： Disclosed herein are various methods of forming metal silicide regions on semiconductor devices. In one example, the method includes forming a sacrificial gate structure above a semiconducting substrate, performing a selective metal silicide formation process to form metal silicide regions in source/drain regions formed in or above the substrate, after forming the metal silicide regions, removing the sacrificial gate structure to define a gate opening and forming a replacement gate structure in the gate opening, the replacement gate structure comprised of at least one metal layer.

    摘要翻译： 本文公开了在半导体器件上形成金属硅化物区域的各种方法。 在一个示例中，该方法包括在半导体衬底之上形成牺牲栅极结构，在形成金属硅化物区域之后，执行选择性金属硅化物形成工艺以形成在衬底中或上方形成的源极/漏极区域中的金属硅化物区域， 牺牲栅极结构以限定栅极开口并在栅极开口中形成替代栅极结构，所述替换栅极结构由至少一个金属层组成。

    Complementary Transistors Comprising High-K Metal Gate Electrode Structures and Epitaxially Formed Semiconductor Materials in the Drain and Source Areas
    30.
    发明申请
    Complementary Transistors Comprising High-K Metal Gate Electrode Structures and Epitaxially Formed Semiconductor Materials in the Drain and Source Areas 有权
    包括高K金属栅电极结构的互补晶体管和排水和源区域中的外延形成的半导体材料

    公开(公告)号：US20120211838A1

    公开(公告)日：2012-08-23

    申请号：US13370944

    申请日：2012-02-10

    申请人： Stephan Kronholz ,  Gunda Beernink ,  Markus Lenski

    发明人： Stephan Kronholz ,  Gunda Beernink ,  Markus Lenski

    IPC分类号： H01L27/092 ,  H01L21/8238

    CPC分类号： H01L21/823807 ,  H01L21/823814

    摘要： When forming sophisticated semiconductor devices including complementary transistors having a reduced gate length, the individual transistor characteristics may be adjusted on the basis of individually provided semiconductor alloys, such as a silicon/germanium alloy for P-channel transistors and a silicon/phosphorous semiconductor alloy forN-channel transistors. To this end, a superior hard mask patterning regime may be applied in order to provide compatibility with sophisticated replacement gate approaches, while avoiding undue process non-uniformities, in particular with respect to the removal of a dielectric cap layer.

    摘要翻译： 当形成包括具有减小的栅极长度的互补晶体管的复杂半导体器件时，可以基于单独提供的半导体合金（例如用于P沟道晶体管的硅/锗合金）和用于磷/磷半导体合金的硅/磷半导体合金 N沟道晶体管。 为此，可以应用优异的硬掩模图案化方案，以提供与复杂的替代栅极方法的兼容性，同时避免不适当的工艺不均匀性，特别是关于去除电介质盖层。