公开(公告)号：US20060280006A1

公开(公告)日：2006-12-14

申请号：US11443770

申请日：2006-05-30

申请人： Hideki Arakawa

发明人： Hideki Arakawa

IPC分类号： G11C5/14

CPC分类号： G11C16/12 ,  G11C5/145 ,  G11C8/08

摘要： The conductance of a first switch circuit (T1) is periodically controlled in response to an error-amplification circuit (A1) whereby electric power, stored in an inductance circuit (L1) from INPUT VOLTAGE VIN, is released, through a rectifier circuit (D1), to a memory cell array (11) for providing BIAS VOLTAGE VPP stepped up to a set voltage value. At this time, a voltage regulating section (13) acts on the error-amplification circuit (A1) of the stepped up voltage supplying section (12) in response to LOCATIONAL INFORMATION AD about a memory cell as a voltage application target of BIAS VOLTAGE VPP and COUNTER INFORMATION COUNT, and directly regulates the voltage value of BIAS VOLTAGE VPP. Even for large storage capacity devices, it is possible to supply a bias voltage stepped up with a sufficient supply capability to the memory cell array (11). It is also possible to supply an optimum stepped up bias voltage by regulation of the set voltage depending on the position of a target memory cell, regardless of the number of target memory cells and their position.

摘要翻译： 响应于误差放大电路（A 1）周期性地控制第一开关电路（T 1）的电导，借此通过整流器释放存储在来自INPUT VOLTAGE VIN的电感电路（L 1）中的电力 电路（D 1）连接到用于提供升高到设定电压值的BIAS电压VPP的存储单元阵列（11）。 此时，电压调节部（13）响应于关于作为BIAS VOLTAGE的电压施加目标的存储单元的位置信息AD而作用于升压电压供给部（12）的误差放大电路（A 1） VPP和COUNTER INFORMATION COUNT，并直接调节BIAS电压VPP的电压值。 即使对于大型存储容量设备，也可以向存储单元阵列（11）提供具有足够的供应能力的偏置电压。 也可以通过根据目标存储器单元的位置调整设定电压来提供最佳的升压偏置电压，而不管目标存储器单元的数量及其位置。

公开(公告)号：US06385088B1

公开(公告)日：2002-05-07

申请号：US08599857

申请日：1996-02-13

申请人： Hideki Arakawa ,  Akira Tanaka ,  Kenshiro Arase ,  Masaru Miyashita

发明人： Hideki Arakawa ,  Akira Tanaka ,  Kenshiro Arase ,  Masaru Miyashita

IPC分类号： G11C1604

CPC分类号： H01L27/115 ,  G11C7/18 ,  G11C16/0416 ,  G11C16/08

摘要： A non-volatile memory device including a plurality of block, each including: a main bit line; a plurality of sub-bit lines to which memory transistors are connected and which are arranged in parallel with respect to the main bit line; and two cascade-connected selection gates which are provided between the main bit line and sub-bit lines and which selectively connect the sub-bit lines.

摘要翻译： 一种包括多个块的非易失性存储器件，每个块包括：主位线; 存储器晶体管连接到并且相对于主位线并行设置的多个子位线; 以及设置在主位线和子位线之间并且有选择地连接子位线的两个级联连接的选择栅极。

公开(公告)号：US5396459A

公开(公告)日：1995-03-07

申请号：US18311

申请日：1993-02-16

申请人： Hideki Arakawa

发明人： Hideki Arakawa

IPC分类号： G11C16/04 ,  G11C16/08 ,  G11C16/26 ,  H01L27/115 ,  H01L29/788 ,  G11C11/40

CPC分类号： H01L29/7885 ,  G11C16/0416 ,  G11C16/08 ,  G11C16/26 ,  H01L27/115 ,  H01L29/7883 ,  G11C2216/28

摘要： A nonvolatile semiconductor memory using a single floating gate transistor, wherein a control gate elecrrode is negatively biased while a source region is positively biased, and a writing operation is performed bit by bit by transferring electrons from the floating gate into the source region through Fowler-Nordheim tunneling. And an erasing operation is performed by injecting channel hot electrons from the drain region into the floating gate, or by injecting electrons from a substrate into the floating gate through Fowler-Nordheim tunneling. The source region is connected to an individual bit line, and the drain region to a common line so that over-erasing is averted.

摘要翻译： 一种使用单个浮栅晶体管的非易失性半导体存储器，其中在源极区域被正偏置的同时，控制栅极电压被负偏置，并且通过将电荷从浮置栅极转移到源极区域中，通过Fowler- Nordheim隧道。 并且通过将沟道热电子从漏极区域注入到浮置栅极中，或者通过Fowler-Nordheim隧道将电子从衬底注入浮栅来执行擦除操作。 源区域连接到单独的位线，并且漏极区域连接到公共线，使得避免过度擦除。

公开(公告)号：US5253200A

公开(公告)日：1993-10-12

申请号：US814582

申请日：1991-12-30

申请人： Hideki Arakawa

发明人： Hideki Arakawa

IPC分类号： G11C16/04 ,  G11C16/08 ,  G11C16/14 ,  G11C8/00 ,  G11C11/34

CPC分类号： G11C16/08 ,  G11C16/0416 ,  G11C16/14

摘要： An electrically erasable programmable nonvolatile memory device includes a plurality of memory cells. The memory device has architecture similar to or the same as an UV-EPROM. Erasure operating is performed by applying a negative voltage to a control gate so as to inject holes into the floating gate.

摘要翻译： 电可擦除可编程非易失性存储器件包括多个存储单元。 存储器件具有与UV-EPROM相似或相似的结构。 通过向控制栅极施加负电压以将空穴注入浮动栅极来执行擦除操作。

公开(公告)号：US5099143A

公开(公告)日：1992-03-24

申请号：US697205

申请日：1991-05-08

申请人： Hideki Arakawa

发明人： Hideki Arakawa

IPC分类号： G11C16/12

CPC分类号： G11C16/12

摘要： An address decoder circuit adapted for enabling electrical erasure in a non-volatile memory without the necessity of numerically increasing the component elements, wherein the direction of application (polarity) of a supply voltage during an erasing operation to a decoding logic gate portion comprising a load MOS transistor and an address input MOS transistor is rendered different from that during a writing or reading operation, and a third potential is applied to the power terminal proximate to the address input MOS transistor and also to the power terminal of a buffer, whereby the third potential is outputted to prevent erasure in the state of non-selection. The resistance of load means is changed to be greater in a writing operation for reducing the power consumption during the writing operation and minimizing the dimensions of component elements. And in a voltage supply circuit, for the purpose of outputting a desired voltage without providing any additional circuit which may consume great power or without causing any level reduction of a first or write voltage, a MOS transistor for outputting the first voltage is controlled in response to a signal obtained by boosting the voltage of a control signal through a voltage multiplier.

公开(公告)号：US4817055A

公开(公告)日：1989-03-28

申请号：US896785

申请日：1986-08-15

申请人： Hideki Arakawa ,  Hiromi Kawashima

发明人： Hideki Arakawa ,  Hiromi Kawashima

IPC分类号： G11C17/00 ,  G05F3/24 ,  G11C5/14 ,  G11C11/34 ,  G11C16/06 ,  G11C16/30 ,  G11C7/00 ,  G11C11/40

CPC分类号： G05F3/24 ,  G11C16/30 ,  G11C5/147

摘要： A semiconductor memory circuit includes therein a bias voltage generator which produces a bias voltage to be supplied to a control gate of a field effect transistor (FET) which forms a part of each memory cell in the semiconductor memory circuit. The bias voltage generator is comprised of a bias voltage generating source which is sandwiched by first and second FET's. The second FET operates to stop a driving current flowing through the bias voltage generating source, in a standby mode, and the first FET operates to produce an output voltage near to the bias voltage. The bias voltage is generated by the bias voltage generating source when both the first and second FET's are turned ON, in an active mode, and the driving current flows therethrough.

摘要翻译： 一种半导体存储器电路，其中包括偏置电压发生器，其产生要提供给在半导体存储器电路中形成每个存储单元的一部分的场效应晶体管（FET）的控制栅极的偏置电压。 偏置电压发生器由偏置电压产生源组成，该偏置电压产生源被第一和第二FET夹在中间。 第二FET在待机模式下操作以停止流过偏置电压产生源的驱动电流，并且第一FET工作以产生接近偏置电压的输出电压。 当第一和第二FET在激活模式下都导通时，偏置电压产生源产生偏置电压，并且驱动电流流过其中。

公开(公告)号：US4703196A

公开(公告)日：1987-10-27

申请号：US763628

申请日：1985-08-08

申请人： Hideki Arakawa

发明人： Hideki Arakawa

IPC分类号： G11C17/00 ,  G11C16/06 ,  G11C16/30 ,  H01L21/8234 ,  H01L21/8247 ,  H01L27/088 ,  H01L29/788 ,  H01L29/792 ,  H02M3/07 ,  H03K17/56 ,  H03K3/01

CPC分类号： H02M3/07 ,  G11C16/30

摘要： A precharging circuit employing ordinary enhancement (E) types MIST'S produces erasing and writing (E-W) voltages to change the data stored in an EEPROM fabricated in a common memory chip with the circuit. The E-W voltage increases gradually from a low level to a high level over a long time interval determined substantially by a long time constant RC circuit, the voltage charge developed on the capacitor C comprising the E-W voltage. The resistor R is implemented by a first MIST connected between a high voltage source and the capacitor C, the gate thereof being controlled by a charge-pump (CP) circuit and a second MIST. The CP circuit is connected between the capacitor C and the gate of the first MIST and is rendered operative during successive clock pulses of a series of clock pulses applied thereto. The CP circuit, during each clock interval, produces a voltage output applied to the first MIST which exceeds the threshold voltage V.sub.th thereof, whereby the first MIST periodically is turned ON for conducting a charging current which flows into the capacitor C. The second MIST is connected between the gate of the first MIST and the capacitor C for suppressing the gate voltage of the first MIST thereby limiting the interval during which the charging current flows therethrough, to a limited portion of each clock pulse interval. The intermittent charging current establishes a long time interval for charging the capacitor C to a value substantially equal to the high voltage source.

摘要翻译： 采用普通增强（E）类型的预充电电路MIST产生擦除和写入（E-W）电压，以用电路改变存储在公共存储器芯片中的EEPROM中存储的数据。 E-W电压基本上由长时间常数RC电路确定的长时间间隔从低电平逐渐增加到在包括E-W电压的电容器C上产生的电压。 电阻器R由连接在高电压源和电容器C之间的第一MIST实现，其栅极由电荷泵（CP）电路和第二MIST控制。 CP电路连接在电容器C和第一MIST的栅极之间，并且在施加到其上的一系列时钟脉冲的连续时钟脉冲期间被操作。 CP电路在每个时钟间隔期间产生施加到超过其阈值电压Vth的第一MIST的电压输出，由此第一MIST周期性地导通，以进行流入电容器C的充电电流。第二MIST是 连接在第一MIST的栅极和电容器C之间，用于抑制第一MIST的栅极电压，从而将充电电流流过的间隔限制到每个时钟脉冲间隔的有限部分。 间歇充电电流建立长时间间隔，用于将电容器C充电到基本上等于高电压源的值。

公开(公告)号：US4682051A

公开(公告)日：1987-07-21

申请号：US706284

申请日：1985-02-27

申请人： Hideki Arakawa

发明人： Hideki Arakawa

IPC分类号： H03K5/08 ,  G01R19/165 ,  G11C7/22 ,  H03K17/22 ,  H03K17/30

CPC分类号： H03K17/223 ,  G01R19/16519 ,  G11C7/22

摘要： A voltage level detection circuit connected between first and second feed lines, including a first depletion-type metal insulator semiconductor (MIS) transistor connected between the first feed line and a common node and having a gate connected to the first feed line, a second depletion-type MIS transistor connected between the common node and the second feed line and having a gate connected to the second feed line, and a circuit connected to the common node for generating an output signal when a potential at the common node reaches a predetermined value. The voltage level detection circuit can include a third depletion-type MIS transistor having a drain connected to the drain of the first depletion-type MIS transistor, a source connected to the source of the first depletion-type MIS transistor, and a gate connected to the output terminal of the output signal generation circuit, to output a stabilized output signal at the output terminal of the output signal generation circuit.

摘要翻译： 连接在第一和第二馈电线之间的电压电平检测电路，包括连接在第一馈电线路和公共节点之间并具有连接到第一馈电线路的栅极的第一耗尽型金属绝缘体半导体（MIS）晶体管， 连接在所述公共节点和所述第二馈电线之间并且具有连接到所述第二馈电线的栅极的电路型MIS晶体管，以及当所述公共节点处的电位达到预定值时连接到所述公共节点的电路，用于产生输出信号。 电压电平检测电路可以包括第三耗尽型MIS晶体管，其漏极连接到第一耗尽型MIS晶体管的漏极，源极连接到第一耗尽型MIS晶体管的源极，栅极连接到 输出信号发生电路的输出端，输出信号发生电路的输出端输出稳定的输出信号。

公开(公告)号：US4677590A

公开(公告)日：1987-06-30

申请号：US844257

申请日：1986-03-24

申请人： Hideki Arakawa

发明人： Hideki Arakawa

IPC分类号： G11C16/04 ,  G11C16/28 ,  G11C11/40

CPC分类号： G11C16/28 ,  G11C16/0433

摘要： A nonvolatile semiconductor memory circuit is provided with a plurality of bit lines and a plurality of word lines. The nonvolatile semiconductor memory cells are located at intersections of the bit lines and word lines and formed by MOS transistors having a floating gate and a control gate therein. A bias circuit supplies a read-out voltage to the control gate of the selected nonvolatile semiconductor memory cell. Sense amplifiers are also included, each having an input which receives read-out data from the selected nonvolatile semiconductor memory cell, and an output which outputs amplified read-out data.A bias circuit is formed by a dummy cell having the same construction as the nonvolatile semiconductor memory cells. A dummy sense amplifier is included having the same construction as the sense amplifiers. A voltage setting circuit is also included, having feedback circuitry connected between the output of the voltage setting circuit and the control gate of the MOS transistor in the dummy cell. Further, in the present invention, depletion-type MOS transistors are used for coupling the gate of the MOS transistor to the bias circuit.

摘要翻译： 非易失性半导体存储器电路设置有多个位线和多个字线。 非易失性半导体存储单元位于位线和字线的交点处，并由其中具有浮动栅极和控制栅极的MOS晶体管形成。 偏置电路向读出的非易失性半导体存储单元的控制栅极提供读出电压。 还包括感测放大器，每个都具有从所选择的非易失性半导体存储单元接收读出数据的输入端和输出放大的读出数据的输出。 偏置电路由具有与非易失性半导体存储单元相同结构的虚设单元形成。 包括具有与读出放大器相同结构的虚拟读出放大器。 还包括电压设定电路，其中反馈电路连接在电压设定电路的输出端和虚设电池中的MOS晶体管的控制栅极之间。 此外，在本发明中，耗尽型MOS晶体管用于将MOS晶体管的栅极耦合到偏置电路。

公开(公告)号：US08599614B2

公开(公告)日：2013-12-03

申请号：US13203612

申请日：2009-04-30

申请人： Takashi Miida ,  Riichiro Shirota ,  Hideki Arakawa ,  Ching Sung Yang ,  Tzung Ling Lin

发明人： Takashi Miida ,  Riichiro Shirota ,  Hideki Arakawa ,  Ching Sung Yang ,  Tzung Ling Lin

IPC分类号： G11C11/34

CPC分类号： G11C16/3427 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/102 ,  G11C16/3418 ,  H01L27/11524 ,  H01L27/11526

摘要： In a programming method for a NAND flash memory device, a self-boosting scheme is used to eliminate excess electrons in the channel of an inhibit cell string that would otherwise cause programming disturb. The elimination is enabled by applying a negative voltage to word lines connected to the inhibit cell string before boosting the channel, and this leads to bringing high program immunity. A row decoder circuitry to achieve the programming operation and a file system architecture based on the programming scheme to improve the efficiency of file management are also described.