公开(公告)号：US20140269732A1

公开(公告)日：2014-09-18

申请号：US13845182

申请日：2013-03-18

Applicant: MELLANOX TECHNOLOGIES LTD.

Inventor： Zachy Haramaty ,  Ran Shani ,  Oded Wertheim

IPC: H04L12/741 ,  H04L12/713

CPC classification number: H04L12/465 ,  H04L12/4654 ,  H04L12/4658

Abstract: A method of communications at an encapsulating bridge includes receiving a packet having an unencapsulated-DA (destination address) and an associated encapsulation identifier. The unencapsulated-DA and the associated encapsulation identifier are used to determine a TxPort-unencapsulated network (unencapsulated network side transmit port) or an encapsulated-DA for the packet. This method reduces latency of processing by reducing lookups, thereby also increasing transmission bandwidth of the communications network. The invention also facilitates embodiments with reduced memory and processing requirements, as compared to conventional implementations. This method is particularly useful for MAC-in-MAC encapsulation.

Abstract translation: 在封装桥接器处的通信方法包括接收具有未封装的DA（目的地地址）和相关联的封装标识符的分组。 未封装的DA和相关联的封装标识符用于确定用于分组的TxPort未封装的网络（未封装的网络侧发送端口）或封装的DA。 该方法通过减少查找来减少处理的延迟，从而也增加通信网络的传输带宽。 与传统实现相比，本发明还有助于减少存储器和处理要求的实施例。 该方法对于MAC-in-MAC封装特别有用。

公开(公告)号：US20240370592A1

公开(公告)日：2024-11-07

申请号：US18309839

申请日：2023-05-01

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Alon Singer ,  Zachy Haramaty

IPC: G06F21/78 ,  G06F21/60

Abstract: A device includes multiple registers, multiple hardware-implemented Privilege Level Indicators (PLIs), and one or more circuits. The registers are to store respective values. The PLIs are to specify privilege levels for accessing the respective registers. The one or more circuits are to perform a secure memory dump operation including (i) checking the PLIs of one or more of the registers and (ii) outputting the values of the registers that are permitted for outputting according to the respective PLIs.

公开(公告)号：US20240289297A1

公开(公告)日：2024-08-29

申请号：US18176089

申请日：2023-02-28

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Zachy Haramaty ,  Yehezkel Rothbaum ,  Amit Solomon ,  Shahar Givony ,  Aviv Hasson

IPC: G06F13/42

CPC classification number: G06F13/4282 ,  G06F2213/0016

Abstract: A system includes a communication bus, a controller device, and a target device. The controller device and the target device may transition between different communication protocols in association with transferring data over the communication bus. The target device may receive a transaction command including a slave address. Based on the slave address, the target device may determine a communication protocol associated with transferring data in association with the transaction command. A first communication protocol may include a message protocol, and the message protocol may be associated with an I2C communication protocol or an I3C communication protocol. The second communication protocol may include a bus protocol, and the bus protocol may be associated with the I2C communication protocol.

公开(公告)号：US20240089211A1

公开(公告)日：2024-03-14

申请号：US18509810

申请日：2023-11-15

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Liron Mula ,  Zachy Haramaty ,  Shachar Bar Tikva ,  Dekel Dadon

IPC: H04L47/32 ,  H04L47/30

CPC classification number: H04L47/32 ,  H04L47/30

Abstract: A relay device is provided that may identify a quantity of empty data byte locations in a data buffer of the relay device. The relay device may receive an indicator associated with transmitting data packets. The relay device may pause or enable a lossless flow of data between the relay device, a host device, and a peer device based on the quantity of empty data byte locations, the indicator, or both. The relay device may include a first data interface coupled with a peer device, a second data interface coupled with a host device, a data buffer configured to store data packets received from the host device, and a state machine that enables a lossless transmission of data between the host device and peer device. The state machine may transmit a pause frame to the host device based on a data buffer utilization reaching a data storage capacity.

公开(公告)号：US20240089194A1

公开(公告)日：2024-03-14

申请号：US17990686

申请日：2022-11-20

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Ariel Almog ,  Eitan Zahavi ,  Idan Burstein ,  Zachy Haramaty ,  Aviv Barnea

IPC: H04L45/00 ,  H04L67/1097 ,  H04L69/22

CPC classification number: H04L45/22 ,  H04L45/66 ,  H04L67/1097 ,  H04L69/22

Abstract: A network adapter includes a port and one or more circuits. The port is to send packets to a network in accordance with a Remote Direct Memory Access over Converged Ethernet (RoCE) protocol. The one or more circuits are to decide whether a packet is permitted to undergo Adaptive Routing (AR) in being routed through the network, to mark the packet with an indication of whether the packet is permitted to undergo AR, and to send the marked packet to the network via the port.

公开(公告)号：US20230047454A1

公开(公告)日：2023-02-16

申请号：US17398677

申请日：2021-08-10

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Liron Mula ,  Zachy Haramaty ,  Shachar Bar Tikva ,  Dekel Dadon

IPC: H04L12/823 ,  H04L12/835

Abstract: A relay device is provided that may identify a quantity of empty data byte locations in a data buffer of the relay device. The relay device may receive an indicator associated with transmitting data packets. The relay device may pause or enable a lossless flow of data between the relay device, a host device, and a peer device based on the quantity of empty data byte locations, the indicator, or both. The relay device may include a first data interface coupled with a peer device, a second data interface coupled with a host device, a data buffer configured to store data packets received from the host device, and a state machine that enables a lossless transmission of data between the host device and peer device. The state machine may transmit a pause frame to the host device based on a data buffer utilization reaching a data storage capacity.

公开(公告)号：US20230004392A1

公开(公告)日：2023-01-05

申请号：US17367367

申请日：2021-07-04

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Zachy Haramaty ,  Yaniv Strassberg ,  Itsik Levi ,  Alon Singer

IPC: G06F9/30 ,  G06F12/02

Abstract: An apparatus includes a processor and split-read control circuitry (SRCC). The processor is to issue a set of one or more split-read requests for loading one or more data values to one or more respective local registers of the processor. The SRCC is to receive the set of one or more split-read requests, to read the one or more data values on behalf of the processor, and to write the data values into the one or more respective local registers. The processor and the SRCC are to coordinate a status of the split-read requests via a split-read-status indication.

公开(公告)号：US09584429B2

公开(公告)日：2017-02-28

申请号：US14335962

申请日：2014-07-21

Applicant: Mellanox Technologies Ltd.

Inventor： Zachy Haramaty ,  Roy Kriss ,  Noam Katz Abramovich ,  George Elias ,  Ran Ravid

IPC: H04L12/801 ,  H04L12/807 ,  H04L12/863 ,  H04L12/825 ,  H04L12/835

CPC classification number: H04L47/39 ,  H04L47/263 ,  H04L47/30

Abstract: A method for communication includes storing packets received from a sending node over a communication link in a receive buffer of a receiving node. The receive buffer includes one or more blocks having a first block size. A first credit count, corresponding to a number of available blocks in the receive buffer, is derived. The first credit count is converted to a second credit count so as to represent an available space in the receive buffer in accordance with a second block size, which is different from the first block size. A transmission rate of the sending node is controlled by publishing the second credit count to the sending node over the communication link.

Abstract translation: 一种用于通信的方法包括：通过接收节点的接收缓冲器中的通信链路存储从发送节点接收的分组。 接收缓冲器包括具有第一块大小的一个或多个块。 导出与接收缓冲器中的多个可用块相对应的第一信用计数。 第一信用计数被转换为第二信用计数，以便根据与第一块大小不同的第二块大小表示接收缓冲器中的可用空间。 发送节点的传输速率通过通过通信链路向发送节点发布第二信用计数来控制。

公开(公告)号：US09582440B2

公开(公告)日：2017-02-28

申请号：US13763676

申请日：2013-02-10

Applicant: Mellanox Technologies Ltd.

Inventor： Freddy Gabbay ,  Amiad Marelli ,  Alon Webman ,  Zachy Haramaty

IPC: G06F13/364

CPC classification number: G06F13/364

Abstract: An apparatus includes multiple data sources and arbitration circuitry. The data sources are configured to send to a common destination data items and respective arbitration requests, such that the data items are sent to the destination regardless of receiving any indication that the data items were served to the destination in response to the respective arbitration requests. The arbitration circuitry is configured to receive and buffer the data items, to perform arbitration on the buffered data items responsively to the arbitration requests, and to serve the buffered data items to the destination in accordance with the arbitration.

Abstract translation: 一种装置包括多个数据源和仲裁电路。 数据源被配置为发送到公共目的地数据项和相应的仲裁请求，使得数据项被发送到目的地，而不管接收到响应于各自的仲裁请求将数据项提供给目的地的任何指示。 仲裁电路被配置为接收和缓冲数据项，以响应于仲裁请求对缓冲的数据项执行仲裁，并且根据仲裁将缓冲的数据项服务到目的地。

公开(公告)号：US20160028613A1

公开(公告)日：2016-01-28

申请号：US14337334

申请日：2014-07-22

Applicant: Mellanox Technologies Ltd.

Inventor： Zachy Haramaty ,  Benny Koren ,  Eitan Zahavi ,  Barak Gafni ,  Tamir Ronen

IPC: H04L12/733 ,  H04L12/721

CPC classification number: H04L45/122 ,  H04L45/14

Abstract: A communication network includes multiple nodes, which are arranged in groups such that the nodes in each group are interconnected in a bipartite topology and the groups are interconnected in a mesh topology. The nodes are configured to convey traffic between source hosts and respective destination hosts by routing packets among the nodes on paths that do not traverse any intermediate hosts other than the source and destination hosts.

Abstract translation: 通信网络包括多个节点，这些节点被分组布置，使得每个组中的节点以二分之一拓扑互连，并且组以网状拓扑互连。 节点被配置为通过在不经过源主机和目的主机之外的任何中间主机的路径上的节点之间路由分组来在源主机和相应的目的主机之间传送流量。